Introduction to PCI protocol

7. Error Detection and Reporting

Parity Generation & Detection — PAR and PERR#

All bus agents are required to generate even parity over the AD and C/BE# busses. The result of the parity calculation appears on the PAR line. Even parity means that the PAR line is set so that the number of bus lines in the logical 1 state, including PAR, is even. All 32 AD lines are always included in the parity calculation even if they are not being used in the current transaction. This is another reason why the driving agent must always drive all 32 AD lines. All agents are required to have the ability to check parity.

The agent driving the AD bus during any clock phase computes even parity and places the result on the PAR line one clock cycle later. The receiving agent checks the parity and, upon detecting an error, may assert PERR#. So on a read transaction, PAR is driven by the target and PERR# is driven by the initiator. The target then senses PERR# and may take action if appropriate. On a write transaction, the opposite occurs.

Figure 13 illustrates the timing of parity generation and detection. The key point to note is that one clock cycle is required to generate parity and another is required to check it. Looking at it in more detail:

Clock

Clock 2. Address phase. The selected master places the target address and command on the bus. All targets latch this information.

Clock 3. Turnaround cycle for read transaction. The master places computed parity for the address phase on PAR.

Clock 4. If any agent has detected a parity error in the address phase it asserts SERR# here. This is the first read data phase and also a turnaround cycle for PAR.

Clock 5. Target places computed parity on PAR. Otherwise this is an idle cycle.

Clock 6. Master reports any parity error here by asserting PERR#.

This also happens to be the address phase for the next transaction.

Clocks 7 to 9 illustrate the same process for write transactions. Note that no turnaround is required on either AD or PAR.

Note that because SERR# is open-drain it may require more than one clock cycle to return to the non-asserted state.

Upon detection of a parity error, the agent that is checking parity must set the DETECTED PARITY ERROR bit in its Configuration Status Register. If the PARITY ERROR RESPONSE bit in its Configuration Command Register is a 1, then it asserts PERR#. Any error recovery strategies are the responsibility of the host attached to the agent that detects the error.

Although bus agents are required to generate parity, there is no requirement that they act on a detected parity error. The ability to detect parity errors and take action is controlled by bits in the device’s Configuration Control Register.

System Errors — SERR#

PERR# only reports parity errors during data phases. That is, it is intended to signal an error condition between a specific master/target pair. Parity is also generated and checked during the address phase. But if there is an error on the address bus, any target which detects a parity error during the address phase asserts SERR# and sets the SIGNALLED SYSTEM ERROR bit in its Status Register if the SERR# ENABLE bit in its Command Register is set. SERR# is an open-drain signal so it is permissible for more than one agent to assert it simultaneously.