Verilog program for Full Adder using dataflow style with select statement

AIM:

Design and verify full adder by using dataflow style with select statement

PROGRAM:

Library ieee;
use ieee.std_logic_1164.all; 
entity fa_select1 is
port(a,b,c:in bit; 
sum,carry:out bit); 
end fa_select1;
architecture df of fa_select1 is begin
with bit_vector'(a,b,c) select (sum,carry)<=bit_vector'("00") when "000" , bit_vector'("10") when "001",
bit_vector'("10") when "010",
bit_vector'("10") when "100",
bit_vector'("01") when "110",
bit_vector'("01") when "011",
bit_vector'("01" )when "101",
bit_vector'("11") when "111"; end df;

SIMULATION OUTPUT:

RESULT: Full adder is simulated and verified