Verilog HDL Program for the function f=x>>3 + x<<4

module sftsum(f,x);
    output [3:0]f;
    input [3:0]x;
    reg [3:0]f;
    reg [3:0]a,b;
    always @ (x)
    begin
        a=x>>3;
        b=x<<4;
        f=a+b;
    end
endmodule