Verilog HDL program for OR Logic gate

The OR gate is a digital logic gate that implements logical disjunction. A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In another sense, the function of OR effectively finds the maximum between two binary digits, just as the complementary AND function finds the minimum.

module or1 (c,a,b);
   output c;
   input a,b;
   assign c=a|b;
Simulated waveform for OR Gate
Simulated waveform for OR Gate
Ansten Lobo

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