Verilog HDL program for Inverter Logic gate

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. An inverter circuit outputs a voltage representing the opposite logic-level to its input.

1
2
3
4
5
module inv(o,a);
    output o;
    input a;
    assign o=!a;
endmodule
Simulated waveform for Inverter
Simulated waveform for Inverter
Ansten Lobo

Leave a Reply

Your email address will not be published. Required fields are marked *

Get the latest updates on your inbox

Be the first to receive the latest updates from Codesdoc by signing up to our email subscription.

    StudentProjects.in