Verilog HDL Program for Counting Number of 1’s in a Vector

module count1(o1,o0,i); // 4-bit vector
output [2:0]o1,o0; // o1: Number of 1’s in vector, o0: Number of 0’s in vector
input [3:0]i;    wire [2:0]o;    wire [3:1]c;
ha u1(o[0],c0,i[0],i[1]);
ha u2(o[1],c1,o[0],i[2]);
ha u3(o[2],c2,o[1],i[3]);
ha u4(c[1],c3,c1,c0);
ha u5(c[2],c[3],c[1],c2);
assign o1={c[3],c[2],o[2]};
pasub31 u6(o0,3'b100,o1);
endmodule
 
module pasub31(d,a,b);//a-b
output [2:0]d;     input [2:0]a;     input [2:0]b;
hs u1(d[0],c1,a[0],b[0]);
fs u2(d[1],c2,a[1],b[1],c1);
fs u3(d[2],c,a[2],b[2],c2);
endmodule