Verilog HDL Program for BCD to GRAY conversion.
1 2 3 4 5 6 7 8 9 10 11 | module bcd2gray(o,i); output [2:0]o; input [2:0]i; reg [2:0]o; always @(i) begin o[2]=i[2]; o[1]=i[2]^i[1]; o[0]=i[1]^i[0]; end endmodule |
Verilog HDL Program for BCD to GRAY conversion.
1 2 3 4 5 6 7 8 9 10 11 | module bcd2gray(o,i); output [2:0]o; input [2:0]i; reg [2:0]o; always @(i) begin o[2]=i[2]; o[1]=i[2]^i[1]; o[0]=i[1]^i[0]; end endmodule |
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