Verilog HDL Program for BCD Adder using Parallel Adder

    module bcdas(s,c,a,b);
    output [3:0]s;
    output c;
    input [3:0]a,b;
    wire [3:0]x;
    wire z,y,co,c1,k;
    parad4 u1(x,c1,a,b);
    and1 u2(y,x[3],x[2]);
    and1 u3(z,x[1],x[3]);
    or1 u4(k,z,y);
    or1 u5(c,k,c1);
    parad4 u6(s,co,x,{1'b0,c,c,1'b0});
endmodule