Verilog program for Full Adder by using dataflow style with select statement

AIM:

Design and verify full adder by using dataflow style with select statement.

PROGRAM:

Library ieee;
use ieee.std_logic_1164.all; entity fa_select is
port(a:in bit_vector(2 downto 0); 
s:out bit_vector(1 downto 0)); end fa_select ;
architecture beh of fa_select is begin
with a select
s<=("00")when"000",
("10")when"001",
("10")when"010",
("01")when"011",
("10")when"100",
("01")when"101",
("01")when"110",
("11")when"111";
end beh; 

SIMULATION OUTPUT:

RESULT: Full adder using dataflow style with select statement is simulated and Verified.