Introduction to PCI protocol

6 Arbitration process under PCI:

Since the PCI Bus accommodates multiple masters — any of which could request the use of the bus at any time — there must be a mechanism that allocates use of bus resources in a reasonable way and resolves conflicts among multiple masters wishing to use the bus simultaneously. Fundamentally, this is called bus arbitration.

The Arbitration Process

Before a bus master can execute a PCI transaction, it must request, and be granted, use of the bus. For this purpose, each bus master has a pair of REQ# and GNT# signals connecting it directly to a central arbiter as shown in Figure 11. When a master wishes to use the bus, it asserts its REQ# signal. Sometime later the arbiter will assert the corresponding GNT# indicating that this master is next in line to use the bus.

Only one GNT# signal can be asserted at any instant in time. The master agent who sees his GNT# asserted may initiate a bus transaction when it detects that the bus is idle. The bus idle state is defined as both FRAME# and IRDY# de-asserted. Figure 12 is a timing diagram illustrating how arbitration works when two masters request use of the bus simultaneously.

Clock

1. Clock -1. The arbiter detects that device A has asserted its REQ#. No one else
   is asserting a REQ# at the moment so the arbiter asserts GNT#-A. In the meantime device B asserts its REQ#.
2. Clock 2. Device A detects its GNT# asserted, the bus is idle and so it asserts FRAME# to begin its transaction. Device A keeps its REQ#
   asserted indicating that it wishes to execute another transaction after this one is complete. Upon detecting REQ#-B asserted, the arbiter
   deasserts GNT#– A and asserts GNT#-B.
3. Clock 3. Device B detects its GNT# asserted but can’t do anything yet because a transaction is in process. Nothing more of interest happens until clock . .
4. Clock 6. Device B detects that the bus is idle because both FRAME# and IRDY# are deasserted. In response, it asserts FRAME# to start its transaction. It also deasserts its REQ# because it does not need a subsequent transaction.
5. Clock 7. The arbiter detects REQ#-B deasserted. In response it deasserts GNT#-B and asserts GNT#-A since REQ#-A is still asserted.

Arbitration is “hidden,” meaning that arbitration for the next transaction occurs at the same time as, or in parallel with, the current transaction. So the arbitration process doesn’t take any time. The specification does not stipulate the nature of the arbitration algorithm or how it is to be implemented other than to say that arbitration must be “fair.” This is not to say that there cannot be a relative priority scheme among masters but rather that every master gets a chance at the bus. Note in Figure 12 that even though Device A wants to execute another transaction, he must wait until Device B has executed his transaction.

Bus Parking:

A master device is only allowed to assert its REQ# when it actually needs the bus to execute a transaction. In other words, it is not allowed to continuously assert REQ# in order to monopolize the bus. This violates the low-latency spirit of the PCI spec. On the other hand, the specification does allow the notion of “bus parking.” The arbiter may be designed to “park” the bus on a default master when the bus is idle. This is accomplished by asserting GNT# to the default master when the bus is idle. The agent on whom the bus is parked can initiate a transaction without first asserting REQ#. This saves one clock. While the choice of a default master is up to the system designer, the specification recommends parking on the last master that acquired the bus.

Chapters:

1. Introduction to PCI protocol
2. PCI Signal Descriptions
3. PCI Bus Transactions
4. PCI Bus Timing Diagrams
5. Configuration space decoding
6. Arbitration process under PCI
7. Error Detection and Reporting

Bibliography

1. PCI Tutorial by Xilinx
2. PCI Bus Demystified by Doug Abbott

Submitted by: Rovin and Sagar