Verilog program | Student Projects

Verilog HDL Program for Random Number Generator

Ansten Lobo — Sat, 09 Jun 2012 10:04:15 +0000

Verilog HDL Program for Random Number Generator.

module tff(q,t,c);
    output q;
    input t,c;
    reg q;
    initial 
     begin 
      q=1'b1;
     end
    always @ (posedge c)
    begin
        if (t==1'b0) begin q=q; end
        else begin q=~q;  end
    end
endmodule

module tff1(q,t,c);
    output q;
    input t,c;
    reg q;
    initial 
     begin 
      q=1'b0;
     end
    always @ (posedge c)
    begin
        if (t==1'b0) begin q=q; end
        else begin q=~q;  end
    end
endmodule

module random(o,clk);
    output [3:0]o;      input clk;
    xor (t0,o[3],o[2]);
    assign t1=o[0];
    assign t2=o[1];
    assign t3=o[2];
    tff u1(o[0],t0,clk);
    tff1 u2(o[1],t1,clk);
    tff1 u3(o[2],t2,clk);
    tff1 u4(o[3],t3,clk);
endmodule

Simulated waveform for Random Number Generator

The post Verilog HDL Program for Random Number Generator first appeared on Student Projects.

Verilog HDL Program for the function f=x>>3 + x

Ansten Lobo — Sat, 09 Jun 2012 10:02:06 +0000

Verilog HDL Program for the function f=x>>3 + x<<4.

module sftsum(f,x);
    output [3:0]f;
    input [3:0]x;
    reg [3:0]f;
    reg [3:0]a,b;
    always @ (x)
    begin
        a=x>>3;
        b=x<<4;
        f=a+b;
    end
endmodule

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Simulated waveform for the function f=x>>3 + x<<4

The post Verilog HDL Program for the function f=x>>3 + x<<4 first appeared on Student Projects.

Verilog HDL Program for Ring Counter

Ansten Lobo — Sat, 09 Jun 2012 09:46:47 +0000

Verilog HDL Program for Ring Counter.

module dff(q,d,c);
    output q;
    input d,c;
    reg q;
    initial   
     q=1'b1; 
    always @ (posedge c)
       q=d;
    endmodule

module dff1(q,d,clk);
    output q;
    input d,clk;
    reg q;
    initial 
    q=1'b0;
    always @ (posedge clk)
    q=d;
endmodule

module ring(q,clk);
    inout [3:0]q;
    input clk;
    dff u1(q[0],q[3],clk);
    dff1 u2(q[1],q[0],clk);
    dff1 u3(q[2],q[1],clk);
    dff1 u4(q[3],q[2],clk);
endmodule

Simulated Waveform for Ring Counter

The post Verilog HDL Program for Ring Counter first appeared on Student Projects.

Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER

Ansten Lobo — Sat, 02 Jun 2012 09:45:10 +0000

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.

module dec38(o,i);
    output [7:0]o;
    input [2:0]i;
    wire x;
    inv u1(x,i[2]);
    decoder24 u2(o[3:0],i[1],i[0],x);
    decoder24 u3(o[7:4],i[1],i[0],i[2]);
endmodule

Simulated waveform for 3-8 Decoder

The post Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER first appeared on Student Projects.

Verilog HDL program for 4-BIT Parallel Adder

Ansten Lobo — Sat, 02 Jun 2012 07:04:44 +0000

A 4 bit binary parallel adder can be formed by cascading four full adder units. The carry of each stage is connected to the next unit as the carry in (That is the third input).

module parad4(a,c,p,q);
    output [3:0]a;
    output c;
    input [3:0]p,q;
    wire c1,c2,c3;
    ha u1(a[0],c1,p[0],q[0]);
    fa u2(a[1],c2,p[1],q[1],c1);
    fa u3(a[2],c3,p[2],q[2],c2);
    fa u4(a[3],c,p[3],q[3],c3);
endmodule

Simulated waveform for Parallel Adder

The post Verilog HDL program for 4-BIT Parallel Adder first appeared on Student Projects.

Verilog HDL Program for HALF ADDER

Ansten Lobo — Thu, 31 May 2012 13:57:20 +0000

The half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on below, incorporates an XOR gate for S and an AND gate for C. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.

Half Adder

module ha(s,co,a,b);
    output s,co;
    input a,b;
    xor1 u1(s,a,b);
    and1 u2 (co,a,b);
endmodule

Simulated waveform for Half Adder

The post Verilog HDL Program for HALF ADDER first appeared on Student Projects.