module primenum3(o,i);
    output o; input [10:0]i; integer k; reg o;
    always @(i)
    begin
    k=i;
    if(i[0]==1'b0)
       begin   o=1'b0; $display("not prime");  end
       else 
       begin
       if(k==3 | k==5 | k==7 | k==11 | k==13 | k==17 | k==19)
       begin  o=1'b1; $display("prime"); end
       else if(k%3==0 | k%5==0 | k%7==0 | k%11==0 | k%13==0 | k%17==0 | k%19==0)
       begin   o=1'b0;  $display("not prime");    end 
       else
       begin   o=1'b1;  $display("prime");        end
       end
        if(i==10'b00 | i==10'b010)
        begin o=1'b1; $display("prime");  end
     end
 endmodule

The post Verilog HDL Program for detecting whether a given number is Prime or not first appeared on Student Projects.

module tff(q,t,c);
    output q;
    input t,c;
    reg q;
    initial 
     begin 
      q=1'b1;
     end
    always @ (posedge c)
    begin
        if (t==1'b0) begin q=q; end
        else begin q=~q;  end
    end
endmodule

module tff1(q,t,c);
    output q;
    input t,c;
    reg q;
    initial 
     begin 
      q=1'b0;
     end
    always @ (posedge c)
    begin
        if (t==1'b0) begin q=q; end
        else begin q=~q;  end
    end
endmodule

module random(o,clk);
    output [3:0]o;      input clk;
    xor (t0,o[3],o[2]);
    assign t1=o[0];
    assign t2=o[1];
    assign t3=o[2];
    tff u1(o[0],t0,clk);
    tff1 u2(o[1],t1,clk);
    tff1 u3(o[2],t2,clk);
    tff1 u4(o[3],t3,clk);
endmodule

The post Verilog HDL Program for Random Number Generator first appeared on Student Projects.

module sftsum(f,x);
    output [3:0]f;
    input [3:0]x;
    reg [3:0]f;
    reg [3:0]a,b;
    always @ (x)
    begin
        a=x>>3;
        b=x<<4;
        f=a+b;
    end
endmodule

The post Verilog HDL Program for the function f=x>>3 + x<<4 first appeared on Student Projects.

module carrysave(s,c,a,b);
    output [3:0]s;
    output c;
    input [3:0]a,b;
    wire [2:0]c2,c0;
    fa u1(s[0],c0[0],a[0],b[0],1'b0);
    dff1 u2(c2[0],c0[0],clk);
    fa u3(s[1],c0[1],a[1],b[1],c2[0]);
    dff1 u4(c2[1],c0[1],clk);
    fa u5(s[2],c0[2],a[2],b[2],c2[1]);
    dff1 u6(c2[2],c0[2],clk);
    fa u7(s[3],c,a[3],b[3],c2[2]);
endmodule

The post Verilog HDL Program for Carry Save Adder first appeared on Student Projects.

module spm(s,m,q);
    output [7:0]s;
    input [3:0]m,q;
    and1 u1(s[0],m[0],q[0]);
    and1 u2(s1,m[0],q[1]);
    and1 u3(s2,m[0],q[2]);
    and1 u4(s3,m[0],q[3]);
    and1 u5(s4,m[1],q[0]);
    and1 u6(s5,m[1],q[1]);
    and1 u7(s6,m[1],q[2]);
    and1 u8(s7,m[1],q[3]);
    and1 u9(s8,m[2],q[0]);
    and1 u10(s9,m[2],q[1]);
    and1 u11(s10,m[2],q[2]);
    and1 u12(s11,m[2],q[3]);
    and1 u13(s12,m[3],q[0]);
    and1 u14(s13,m[3],q[1]);
    and1 u15(s14,m[3],q[2]);
    and1 u16(s15,m[3],q[3]);
    parad4 u21({s18,s17,s16,s[1]},c3,{s7,s6,s5,s4},{1'b0,s3,s2,s1});
    parad4 u22({s21,s20,s19,s[2]},c7,{c3,s18,s17,s16},{s11,s10,s9,s8});
    parad4 u23({s[6],s[5],s[4],s[3]},s[7],{c7,s21,s20,s19},{s15,s14,s13,s12});
endmodule

module parad4(a,c,p,q); // Parallel Adder Module
    output [3:0]a;     output c;     input [3:0]p,q;    wire c1,c2,c3;
    ha u1(a[0],c1,p[0],q[0]);
    fa u2(a[1],c2,p[1],q[1],c1);
    fa u3(a[2],c3,p[2],q[2],c2);
    fa u4(a[3],c,p[3],q[3],c3);
endmodule

The post Verilog HDL Program for Serial Parallel Multiplier first appeared on Student Projects.

module mod10(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1(qc,q3);
    inv u2(qb,q1);
    inv u3(qa,q0);
    and1 u4(j3,q1,q0,q2);
    assign k3=q0;
    and1 u5(k2,q1,q0);
    assign j2=k2;
    and1 u6(j1,qc,q0);
    assign k1=q0;
    assign j0=1'b1;
    assign k0=1'b1;
    jk1 u11(qo[0],j0,k0,clk);
    jk1 u12(qo[1],j1,k1,clk);
    jk1 u13(qo[2],j2,k2,clk);
    jk1 u14(qo[3],j3,k3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule

The post Verilog HDL Program for Decade Counter first appeared on Student Projects.

module mod13(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1 (qd,q3);
    inv u2(qc,q2);
    and1 u3 (a,q1,q0,q2);
    and1 u4(b,q3,q2);
    or1 u5(t3,a,b);
    and1 u6(c,q1,q0);
    and1 u7(d,q3,q2);
    or1 u8(t2,c,d);
    assign t1=q0;
    or1 u9(t0,qd,qc);
    tff u10(qo[0],t0,clk);
    tff u12(qo[1],t1,clk);
    tff u13(qo[2],t2,clk);
    tff u14(qo[3],t3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule

The post Verilog HDL Program for Mod-13 Counter first appeared on Student Projects.

module johnson(q,clk);
    output [3:0]q;
    input clk;
    not (qc,q[0]);
    dff u1(q[3],qc,clk);
    dff1 u2(q[2],q[3],clk);
    dff1 u3(q[1],q[2],clk);
    dff1 u4(q[0],q[1],clk);
endmodule

The post Verilog HDL Program for Johnson Counter first appeared on Student Projects.

module dff(q,d,c);
    output q;
    input d,c;
    reg q;
    initial   
     q=1'b1; 
    always @ (posedge c)
       q=d;
    endmodule

module dff1(q,d,clk);
    output q;
    input d,clk;
    reg q;
    initial 
    q=1'b0;
    always @ (posedge clk)
    q=d;
endmodule

module ring(q,clk);
    inout [3:0]q;
    input clk;
    dff u1(q[0],q[3],clk);
    dff1 u2(q[1],q[0],clk);
    dff1 u3(q[2],q[1],clk);
    dff1 u4(q[3],q[2],clk);
endmodule

The post Verilog HDL Program for Ring Counter first appeared on Student Projects.

 
module sipo(sout,sin,clk);
    output [3:0]sout;
    input sin,clk;
    dff2 u1(sout[0],sin,clk);
    dff2 u2(sout[1],sout[0],clk);
    dff2 u3(sout[2],sout[1],clk);
    dff2 u4(sout[3],sout[2],clk);
endmodule

The post Verilog HDL Program for Serail In – Parallel Out Shift Register first appeared on Student Projects.