module mod10(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1(qc,q3);
    inv u2(qb,q1);
    inv u3(qa,q0);
    and1 u4(j3,q1,q0,q2);
    assign k3=q0;
    and1 u5(k2,q1,q0);
    assign j2=k2;
    and1 u6(j1,qc,q0);
    assign k1=q0;
    assign j0=1'b1;
    assign k0=1'b1;
    jk1 u11(qo[0],j0,k0,clk);
    jk1 u12(qo[1],j1,k1,clk);
    jk1 u13(qo[2],j2,k2,clk);
    jk1 u14(qo[3],j3,k3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule

The post Verilog HDL Program for Decade Counter first appeared on Student Projects.

module mod13(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1 (qd,q3);
    inv u2(qc,q2);
    and1 u3 (a,q1,q0,q2);
    and1 u4(b,q3,q2);
    or1 u5(t3,a,b);
    and1 u6(c,q1,q0);
    and1 u7(d,q3,q2);
    or1 u8(t2,c,d);
    assign t1=q0;
    or1 u9(t0,qd,qc);
    tff u10(qo[0],t0,clk);
    tff u12(qo[1],t1,clk);
    tff u13(qo[2],t2,clk);
    tff u14(qo[3],t3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule

The post Verilog HDL Program for Mod-13 Counter first appeared on Student Projects.

module johnson(q,clk);
    output [3:0]q;
    input clk;
    not (qc,q[0]);
    dff u1(q[3],qc,clk);
    dff1 u2(q[2],q[3],clk);
    dff1 u3(q[1],q[2],clk);
    dff1 u4(q[0],q[1],clk);
endmodule

The post Verilog HDL Program for Johnson Counter first appeared on Student Projects.

 
module sipo(sout,sin,clk);
    output [3:0]sout;
    input sin,clk;
    dff2 u1(sout[0],sin,clk);
    dff2 u2(sout[1],sout[0],clk);
    dff2 u3(sout[2],sout[1],clk);
    dff2 u4(sout[3],sout[2],clk);
endmodule

The post Verilog HDL Program for Serail In – Serial Out Shift Register first appeared on Student Projects.

module sr2t(q,q1,t,clk);
output q,q1;
input t,clk;
wire x,y;
and1 u1(x,t,q1);
and1 u2(y,t,q);
srff u3(q,q1,y,x,clk); //srff u(q,q1,r,s,clk);
endmodule

The post Verilog HDL Program for T flip flop using RS flip flop first appeared on Student Projects.

	module sr2jk(q,q1,j,k,clk);
	output q,q1;
	input j,k,clk;
	and1 u1(w,j,q1);
	inv u4(k1,k);
	and1 u2(x,k1,q);
	srff u3(q,q1,x,w,clk);
	endmodule

The post Verilog HDL Program for JK flip flop using RS flip flop first appeared on Student Projects.

If the T input is high, the T flip-flop changes state (“toggles”) whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value.

module t(q,q1,t,c);
output q,q1;
input t,c;
reg q,q1;
initial 
   begin 
	q=1'b1;
	q1=1'b0;
   end
 always @ (c)
	begin
		if(c)
			 begin
			   if (t==1'b0) begin q=q; q1=q1; end
			   else begin q=~q; q1=~q1; end
			 end
	 end
endmodule    

The post Verilog HDL Program for T Flip Flop first appeared on Student Projects.

he D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

module d(q,q1,d,c);
output q,q1;
 input d,c;
 reg q,q1;
	initial 
	   begin
		   q=1'b0; q1=1'b1;
	  end
	always @ (posedge c)
	   begin 
		 q=d;
		 q1= ~d;
	   end
endmodule

The post Verilog HDL Program for D Flip Flop first appeared on Student Projects.

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

module srff(q,q1,r,s,clk);
	output q,q1;
	input r,s,clk;
	reg q,q1;
	initial
	begin
		q=1'b0;
		q1=1'b1;
	end
	always @(posedge clk)
	  begin
	  case({s,r})
		 {1'b0,1'b0}: begin q=q; q1=q1; end
		 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
		 {1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
		 {1'b1,1'b1}: begin q=1'bx; q=1'bx; end
	endcase
	end
endmodule

The post Verilog HDL Program for R-S Flip Flops first appeared on Student Projects.

    module bcdas(s,c,a,b);
    output [3:0]s;
    output c;
    input [3:0]a,b;
    wire [3:0]x;
    wire z,y,co,c1,k;
    parad4 u1(x,c1,a,b);
    and1 u2(y,x[3],x[2]);
    and1 u3(z,x[1],x[3]);
    or1 u4(k,z,y);
    or1 u5(c,k,c1);
    parad4 u6(s,co,x,{1'b0,c,c,1'b0});
endmodule

The post Verilog HDL Program for BCD Adder using Parallel Adder first appeared on Student Projects.