HDL | Student Projects

Verilog HDL Program for Decade Counter

Ansten Lobo — Sat, 09 Jun 2012 09:52:53 +0000

Verilog HDL Program for Decade Counter.

module mod10(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1(qc,q3);
    inv u2(qb,q1);
    inv u3(qa,q0);
    and1 u4(j3,q1,q0,q2);
    assign k3=q0;
    and1 u5(k2,q1,q0);
    assign j2=k2;
    and1 u6(j1,qc,q0);
    assign k1=q0;
    assign j0=1'b1;
    assign k0=1'b1;
    jk1 u11(qo[0],j0,k0,clk);
    jk1 u12(qo[1],j1,k1,clk);
    jk1 u13(qo[2],j2,k2,clk);
    jk1 u14(qo[3],j3,k3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule

Simulated Waveform for Decade Counter

The post Verilog HDL Program for Decade Counter first appeared on Student Projects.

Verilog HDL Program for Parallel In – Serial Out Shift Register

Ansten Lobo — Sat, 09 Jun 2012 09:35:45 +0000

Verilog HDL Program for Parallel In – Serial Out Shift Register.

module piso1(sout,sin,clk);
    output sout;
    input [3:0]sin;
    input clk;
    wire [3:0]q;
    inv u1(p,sl);
    and1 u2(n,sin[1],p);
    and1 u3(r,sl,q[0]);
    or1 u4(s,n,r);
    and1 u5(t,sin[2],p);
    and1 u6(u,sl,q[1]);
    or1 u7(v,u,t);
    and1 u8(w,sin[3],p);
    and1 u9(y,sl,q[2]);
    or1 u10(z,w,y);
    dff1 u11(q[0],sin[0],clk);
    dff1 u12(q[1],s,clk);
    dff1 u13(q[2],v,clk);
    dff1 u14(q[3],z,clk);
    assign sout = q[3];
endmodule

Simulated Waveform for Parallel In – Serial Out Shift Register

The post Verilog HDL Program for Parallel In – Serial Out Shift Register first appeared on Student Projects.

Verilog HDL Program for D flip flop using RS flip flop

Ansten Lobo — Sat, 09 Jun 2012 09:23:49 +0000

Verilog HDL Program for D flip flop using RS flip flop.

module sr2d(q,q1,d,clk);
output q,q1;
input d,clk;
wire x;
inv u1(x,d);
srff u2(q,q1,x,d,clk); //srff u(q,q1,r,s,clk);
endmodule

Simulated Waveform for D flip flop using RS flip flop

The post Verilog HDL Program for D flip flop using RS flip flop first appeared on Student Projects.

Verilog HDL Program for NOR Logic Gate

Ansten Lobo — Thu, 31 May 2012 13:38:46 +0000

The NOR gate is a digital logic gate that implements logical NOR. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation—combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.

module nor1(c,a,b);
    output c;
    input a,b;
    wire d;
    or1 u1(d,a,b);
    inv u2(c,d);
endmodule

Simulated waveform for Nor Gate

The post Verilog HDL Program for NOR Logic Gate first appeared on Student Projects.

Verilog HDL program for AND Logic gate

Ansten Lobo — Thu, 31 May 2012 13:25:38 +0000

The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively finds the minimum between two binary digits, just as the OR function finds the maximum. Therefore, the output is always 0 except when all the inputs are 1s.

module and1(c,a,b);
    output c;
    input a,b;
    assign c=a&b;
endmodule

Simulated waveform for And Gate

The post Verilog HDL program for AND Logic gate first appeared on Student Projects.

Verilog HDL program for Inverter Logic gate

Ansten Lobo — Thu, 31 May 2012 12:55:27 +0000

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. An inverter circuit outputs a voltage representing the opposite logic-level to its input.

module inv(o,a);
    output o;
    input a;
    assign o=!a;
endmodule

Simulated waveform for Inverter

The post Verilog HDL program for Inverter Logic gate first appeared on Student Projects.