<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>2-4decoder | Student Projects</title>
	<atom:link href="https://studentprojects.in/tag/2-4decoder/feed/" rel="self" type="application/rss+xml" />
	<link>https://studentprojects.in</link>
	<description>Microcontroller projects, Circuit Diagrams, Project Ideas</description>
	<lastBuildDate>Sat, 09 Jun 2012 08:53:55 +0000</lastBuildDate>
	<language>en-US</language>
	<sy:updatePeriod>
	hourly	</sy:updatePeriod>
	<sy:updateFrequency>
	1	</sy:updateFrequency>
	<generator>https://wordpress.org/?v=6.1.7</generator>
	<item>
		<title>Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-3-8-decoder-using-2-4-decoder/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-3-8-decoder-using-2-4-decoder/#comments</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 02 Jun 2012 09:45:10 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[3-8 decoder]]></category>
		<category><![CDATA[2-4decoder]]></category>
		<category><![CDATA[Verilog program]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3026</guid>

					<description><![CDATA[<p>A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-3-8-decoder-using-2-4-decoder/">Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.</p>
<pre lang="VHDL" line="1">
module dec38(o,i);
    output [7:0]o;
    input [2:0]i;
    wire x;
    inv u1(x,i[2]);
    decoder24 u2(o[3:0],i[1],i[0],x);
    decoder24 u3(o[7:4],i[1],i[0],i[2]);
endmodule
</pre>
<figure id="attachment_3027" aria-describedby="caption-attachment-3027" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-waveform-for-3-8-Decoder.jpg" alt="Simulated waveform for 3-8 Decoder" title="Simulated waveform for 3-8 Decoder" width="615" height="64" class="size-full wp-image-3027" /><figcaption id="caption-attachment-3027" class="wp-caption-text">Simulated waveform for 3-8 Decoder</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-3-8-decoder-using-2-4-decoder/">Verilog HDL Program for 3-8 DECODER USING 2-4 DECODER</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
					<wfw:commentRss>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-3-8-decoder-using-2-4-decoder/feed/</wfw:commentRss>
			<slash:comments>2</slash:comments>
		
		
			</item>
	</channel>
</rss>
