Design and Verification of a PCI Based System using SystemC

3.Verification environment

3.1 Introduction

This verification describes in detail about the verification of the PCI protocol Model.

The entire verification of all the PCI bus commands are divided into :

1. Write transactions
2. Read transactions
3. Wait state transactions
4. Transaction terminations

The verification environment setup is same for all the transactions, as described in the section-‘verification environment details’.

3.2 Scope of the verification

This test is intended only for the behavioral verification of the design. Only the chip level of abstraction is used for the verification. This verification is for a TLM model, it cannot be used to verify the RTL level or gate level details of the design.

The verification tests written for the design can be used to verify the design at the cycle level. This is achieved by repeated read and write transactions into the DUT and then by viewing the trace file generated by the simulation kernel.

3.3 Assumptions made

These tests assume the following:

1. The I/O and Memory Spaces are kept in the monitor using the dynamic memory allocation. This space is 256 bytes long.
2. Once the master has started the transaction, no information packet sent until the end of the transaction.
3. The slave address is sent during the instantiation of the slave.

3.4 Verification environment details

The verification environment contains the following components:

1. The DUT or the Device Under Test, which is the object to be verified. It contains
   1. Three master instants.
   2. Six slave instants
   3. One arbiter
2. The driver module which writes the packets of test data into the channel of DUT. Internally, it contains an SC_THREAD process called send().
3. The send function in the testbench sends the slave address, data, PCI command, data length, master number.
4. One monitor module which reads out data from the slave through the channel and displays it into the console. The process associated with this module is monitor ().
5. SystemC clock object is sc_clock. This clock is fed into the clock input of the master and slave with a frequency of 33 nano seconds.
6. vcd trace file: the dump file used by the systemC simulation kernel to dump the trace information.

3.5 Tools used for verification

1. g++
2. Dinotrace (VCD viewer)
3. SystemC 2.0.1

3.6 Verifying the PCI transaction

Features to be verified:

1. Write Transaction:
2. Read transaction
3. Wait states transaction
4. Transaction termination
5. Error reporting transactions

Write transaction:

For the write transaction driver sends the write PCI command, it may be I/O write, Memory write, Configuration write or Memory write and invalidate. Initially using Configuration write, the configuration base address register is configured. After the configuration is over, the master gets the information packet from the testbench and then it places the address on the PCI bus. If the address matches then the respective slave claims the transaction. The received data in the slave is sent to the monitor and data will be kept in the respective destination space. For multiple write transaction the data length is obtained from the driver along with the information packet. For the multiple write transactions, the slave keeps the data in destination space of respective I/O or Memory space as given in the address.
At the end of the transaction, the sent data and received data in the monitor are compared. If they do not match an error message displayed in the Monitor.

Test case description:

1. I/O write : For this test case the driver sends the information packet containing slave address, data, master of the transaction and command = 3. When the information packet is written to the corresponding master, the master writes the data during data phase to the slave. The slave writes this data in to the I/O Address space in the monitor.
2. Memory write : For this test case the driver sends the information packet containing slave address, data, master of the transaction and command = 7. When the information packet is written to the corresponding master, the master writes the data during data phase to the slave. The slave writes this data in to the Memory Address space in the monitor.
3. Configuration write : For this test case the driver sends the information packet containing slave address, data, master of the transaction and command = 11.When the information packet is written to the corresponding master, the master writes the data during data phase to the slave. The slave writes this data in to the Configuration Address space in the slave. During Configuration write the IDSEL signal is asserted.
4. Memory write and Invalidate : For this test case the driver sends the information packet containing slave address, data, data length, master of the transaction and command = 7. When the information packet is written to the corresponding master, the master writes the data during data phase to the slave. The slave writes this data in to the Memory Address space in the monitor according to its data length.
5. Multiple Master Write: In this test case more than one masters requesting for the write command for the same slave. The arbiter gives the grant signal to the master with the higher priority. The selected master begins the transaction. When the transaction is over the grant goes to the next requesting master.

For the above test cases, the sent and the received data are compared at the end of every transaction. An error message is displayed if any error is found.

Read transaction:

For the read transaction driver sends the read PCI command, it may be I/O read, Memory read, Configuration read, Memory read multiple or Memory read line. Initially using Configuration write, the configuration base address register is configured. After the configuration is over, the master gets the information packet from the testbench and then it places the address on the PCI bus. If the address matches then the respective slave claims the transaction. The slave fetches the data from the respective destination space given in the address and places this data during the data phase on the PCI bus. The received data in the master is sent to the driver and data will be stored in an array. For multiple read transactions the data length is obtained from the driver along with the information packet. For the multiple read transactions, the slave keeps the data from the destination space and places it on the PCI bus during the data phase. Similarly the received and sent data are compared for an error.

Test case description:

1. I/O read : For this test case the driver sends the information packet containing slave address, data, master of the transaction and command = 2.
   When the information packet is written to the corresponding master, the master writes the address of the slave during the address phase. Then the corresponding slave reads data from the I/O Address space in the monitor. This data in turn sent back to the master and then to the driver.
2. Memory read: For this test case the driver sends the information packet containing slave address, master of the transaction and command = 6. When the information packet is written to the corresponding master, the master writes the address during address phase to the corresponding slave. The slave reads the data from the Memory Address space in the monitor. This data in turn sent back to the master and then to the driver.
3. Configuration read: For this test case the driver sends the information packet containing slave address, master of the transaction and command = 10. When the information packet is written to the corresponding master, the master writes the address to the corresponding slave during address phase. Then slave reads the data from the Configuration Address space in the slave. This data in turn sent back to the master and then to the driver.
4. Memory read multiple : For this test case the driver sends the information packet containing slave address, data length, master of the transaction and command = 12. When the information packet is written to the corresponding master, the master writes the address during address phase to the slave. The corresponding slave reads the data from the Memory Address space in the monitor according to its data length. This data in turn sent back to the master and then to the driver. The reading continues till the last data phase.
5. Memory read line : For this test case the driver sends the information packet containing slave address, master of the transaction and command = 14. When the information packet is written to the corresponding master, the master writes the address during address phase to the slave. The corresponding slave reads the full cacheline data of the Memory Address space in the monitor. This data in turn sent back to the master and then to the driver
6. Multiple Master read: In this test case more than one masters requesting for the read command for the same slave. The arbiter gives the grant signal to the master with the higher priority. The selected master begins the transaction. When the transaction is over the grant goes to the next requesting master.

For the above test cases, the sent and the received data are compared at the end of every transaction. An error message is displayed if any error is found.

Wait state transaction

During any PCI transaction, when both master and slave are committed to complete a transaction, in case if either of them want to delayed the transaction by deasserting the TRDY or IRDY pin. When both IRDY and TRDY asserted the data transfer continues. The assertion and deassertion of TRDY or IRDY signal is done on the falling clock edge. The driver sends the information to the slave to insert an wait state using the “Abort()”
Function. Similarly the driver sends the information to the master to insert a wait state using the “send()” function.

Test case description:

1. Master inserted wait state: In this test case the driver sends either a multiple read or a write transaction command to the master. When the transaction is going on the driver sends the wait state command for the IRDY to go high for a specified number of clock cycles. The wait bit in the channel is set, the master inserts the wait state.
2. Slave inserted wait state: In this test case the driver sends either a multiple read or a write transaction command to the master. When the transaction is being carried out, the driver sends the wait state command to the slave for the TRDY to go high for a specified number of clock cycles. This is accomplished by using the function “Abort( )”.

In the above test case when ever the wait state is inserted the transfer of data is suspended, when the wait states are removed the transfer of data resumes.

Transaction termination:

There are two types of transaction terminations.

1. Master initiated termination
   1. Master abort
2. Target initiated termination
   1. Target Abort
   2. Target abort with data
   3. Target abort without data
   4. Retry

1. Master abort: this termination occurs when ever the master refers to a invalid slave address. This is done by sending a invalid slave address from the driver. If master abort occurs then no transaction takes place.
2. Target abort: this termination occurs when the slave is unable to carry out the current transaction. The abort function sends the information to the slave from the driver, for target abort condition.
3. Target abort with data: this termination occurs when the slave is unable to carry out the current transaction but it can accept only one data. The abort function sends the information to the slave from the driver, for target abort with data condition.
4. Target abort without data: this termination occurs when the slave is unable to carry out the current transaction and cannot accept any data. The abort function sends the information to the slave from the driver, for target abort without data condition.
5. Retry: this is termination occurs when TRDY is not asserted. the abort function informs the slave to carry out the retry operation.
6. When the slave terminates with retry the master will again restart the same transaction again.

Error reported terminations:

Parity error: this occurs when there is a parity error on AD, C/BE, and parity signal. The parity error is generated by manipulating the PAR signal.

During a master read the PAR signal is altered by the Slave, the abort function in driver sends the information to do so. If parity error occurs then target abort takes place. During master write the parity error is signaled by the driver by setting wait bit=2. When wait bit=2 the master alters the PAR signal to generate the parity error condition. During a write transaction parity error condition results in master abort.

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