1. Overview

Signaling System No. 7 is a global standard for telecommunications defined by the International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T). The standard defines the procedures and protocol by which network elements in the public switched telephone network (PSTN) exchange information over a digital signaling network to effect wireless (cellular) and wire line call setup, routing and control. The ITU definition of SS7 allows for national variants such as North America’s American National Standards Institute (ANSI) and Bell Communications research (Telcordia Technologies) standards and Europe’s European Telecommunications Standards Institute (ETSI) standard.

The SS7 network and protocol are used for:

• Local number portability (LNP)
• Toll-free (800/888) and toll (900) wire line services
• Enhanced call features such as call forwarding, calling party name/number display and three-way calling.
• Efficient and secure worldwide telecommunications
• Basic call setup, management and tear down
• Wireless services such as personal communications services (PCS), wireless roaming and Mobile subscriber authentication

1.a Signaling Links

SS7 messages are exchanged between network elements over 56 or 64 kilobit per second (kbps) bidirectional channels called signaling links. Signaling occurs out-of-band on dedicated channels rather than in-band on voice channels. Compared to in-band signaling, out-of-band signaling provides:

• Faster call setup times (compared to in-band signaling using multi-frequency (MF)
  signaling tones)
• More efficient use of voice circuits
• Support for Intelligent Network (IN) services, which require signaling to network
  elements without voice trunks (e.g., database systems)
• Improved control over fraudulent network usage

1.b Signaling Points

Each signaling point in the SS7 network is uniquely identified by a numeric point code. Point codes are carried in signaling messages exchanged between signaling points to identify the source and destination of each message. Each signaling point uses a routing table to select the appropriate signaling path for each message.

There are three kinds of signaling points in the SS7 network.

• SSP (Service Switching Point)
• STP (Signal Transfer Point)
• SCP (Service Control Point)

SSPs are switches that originate, terminate or tandem calls. An SSP sends signaling messages to other SSPs to setup, manage and release voice circuits required to complete a call. An SCP sends a response to the originating SSP containing the routing number(s) associated with the dialed number. An alternate routing number may be used by the SSP if the primary number is busy or the call is unanswered within a specified time. Actual call features vary from network to network and from service to service.

Network traffic between signaling points may be routed via a packet switch called an STP. An STP routes each incoming message to an outgoing signaling link based on routing information contained in the SS7 message. Because it acts as a network hub, an STP provides improved utilization of the SS7 network by eliminating the need for direct links between signaling points.

Links between signaling points are also provisioned in pairs. Traffic is shared across all links in the linkset. If one of the links fails, the signaling traffic is rerouted over another link in the linkset.

1.c SS7 Signaling Link Types

Signaling links are logically organized by link type (“A” through “F”) according to their use in the SS7
signaling network.

A Link: An “A” (access) link connects a signaling end point (e.g., an SCP or SSP) to an STP. Only
messages originating from or destined to the signaling end point are transmitted on an “A” link.

B Link: A “B” (bridge) link connects one STP to another. Typically, a quad of “B” links interconnect
peer (or primary) STP (e.g., the STPs from one network to the STPs of another network). The distinction between a “B” link and a “D” link is rather arbitrary. For this reason, such links may be referred to as “B/D” links.

C Link: A “C” (cross) link connects STPs performing identical functions into a mated pair. A “C” link is
used only when an STP has no other route available to a destination signaling point due to link failure(s). Note that SCPs may also be deployed in pairs to improve reliability; unlike STPs however, mated SCPs are not interconnected by signaling links.

D Link: A “D” (diagonal) link connects a secondary (e.g., local or regional) STP pair to a primary (e.g,
Inter-network gateway) STP pair in a quad-link configuration. Secondary STPs within the same network are connected via a quad of “D” links. The distinction between a “B” link and a “D” link is rather arbitrary. For this reason, such links may be referred to as “B/D” links.

E Link: An “E” (extended) link connects an SSP to an alternate STP. “E” links provide an alternate
signaling path if an SSP’s “home” STP cannot be reached via an “A” link. “E” links are not
usually provisioned unless the benefit of a marginally higher degree of reliability justifies the
added expense.

F Link: An “F” (fully associated) link connects two signaling end points (i.e., SSPs and SCPs). “F”
links are not usually used in networks with STPs. In networks without STPs, “F” links directly
connect signaling points.

2. SS7 Protocol Stack

The hardware and software functions of the SS7 protocol are divided into functional abstractions called
“levels.” These levels map loosely to the Open Systems Interconnect (OSI) 7-layer model defined by
the International Standards Organization (ISO).

2.a Message Transfer Part

The Message Transfer Part (MTP) is divided into three levels.

The lowest level, MTP Level 1, is equivalent to the OSI Physical Layer. MTP Level 1 defines the physical, electrical and functional characteristics of the digital signaling link. Physical interfaces defined include E-1 (2048 kb/s; 32 64 kb/s channels), DS-1 (1544 kb/s; 24 64kb/s channels), V.35 (64 kb/s), DS-0 (64 kb/s) and DS-0A (56 kb/s).

MTP Level 2 ensures accurate end-to-end transmission of a message across a signaling link. Level 2 implements flow control, message sequence validation and error checking. When an error occurs on a signaling link, the message (or set of messages) is retransmitted. MTP Level 2 is equivalent to the OSI Data Link Layer

MTP Level 3 provides message routing between signaling points in the SS7 network. MTP Level 3 reroutes traffic away from failed links and signaling points and controls traffic when congestion occurs. MTP Level 3 is equivalent to the OSI Network Layer.

2.b ISDN User Part (ISUP)

The ISDN User Part (ISUP) defines the protocol used to set-up, manage and release trunk circuits that carry voice and data between terminating line exchanges (e.g., between a calling party and a called party). ISUP is used for both ISDN and non-ISDN calls. However, calls that originate and terminate at the same switch do not use ISUP signaling.

2.c Telephone User Part (TUP)

In some parts of the world, the Telephone User Part (TUP) is used to support basic call setup and tear-down. TUP handles analog circuits only. In many countries, ISUP has replaced TUP for call management.

2.d Signaling Connection Control Part (SCCP)

SCCP provides connectionless and connection-oriented network services and global title translation (GTT) capabilities above MTP Level 3. A global title is an address (e.g., a dialed 800 number, calling card number or mobile subscriber identification number) that is translated by SCCP into a destination point code and subsystem number. A subsystem number uniquely identifies an application at the destination signaling point. SCCP is used as the transport layer for TCAP-based services.

2.e Transaction Capabilities Applications Part (TCAP)

TCAP supports the exchange of non-circuit related data between applications across the SS7 network using the SCCP connectionless service. Queries and responses sent between SSPs and SCPs are carried in TCAP messages.

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In response to this need, PCI (peripheral component interconnect) has emerged as the dominant mechanism for interconnecting the elements of modern, high performance computer systems. It is a well thought out standard with a number of forward looking features that should keep it relevant well into the next century. Originally conceived as a mechanism for interconnecting peripheral components on a motherboard, PCI has evolved into at least a half dozen different physical implementations directed at specific market segments yet all using the same basic bus protocol. In the form known as Compact PCI, it is having a major impact in the rapidly growing telecommunications market.

PCI offers a number of significant performance and architectural advantages over previous busses:

Speed:The basic PCI protocol can transfer up to 132 Mbytes per second, well over an order of magnitude faster than ISA. Even so, the demand for bandwidth is insatiable. Extensions to the basic protocol yield bandwidths as high as 512 Mbytes per second and development currently under way will push it to a gigabyte.

Configurability:PCI offers the ability to configure a system automatically, relieving the user of the task of system configuration. It could be argued that PCI’s success owes much to the very fact that users need not be aware of it.

Multiple Masters:Prior to PCI, most busses supported only one “master,” the processor. High bandwidth devices could have direct access to memory through a mechanism called DMA (direct memory access) but devices, in general, could not talk to each other. In PCI, any device has the potential to take control of the bus and initiate transactions with any other device.

Reliability:“Hot Plug” and “Hot Swap,” defined respectively for PCI and Compact PCI, offer the ability to replace modules without disrupting a system’s operation. This substantially reduces MTTR (mean time to repair) to yield the necessary degree of up-time required of mission-critical systems such as the telephone network.

1. PCI Protocol

PCI is a synchronous bus architecture with all data transfers being performed relative to a system clock (CLK). The initial PCI specification permitted a maximum clock rate of 33 MHz allowing one bus transfer to be performed every 30 nanoseconds. Later, PCI specification extended the bus definition to support operation at 66 MHz, but the vast majority of today’s personal computers continue to implement a PCI bus that runs at a maximum speed of 33 MHz.

PCI implements a 32-bit multiplexed Address and Data bus (AD[31:0]). It architects a means of supporting a 64-bit data bus through a longer connector slot, but most of today’s personal computers support only 32-bit data transfers through the base 32-bit PCI connector. At 33 MHz, a 32-bit slot supports a maximum data transfer rate of 132 MBytes/sec, and a 64-bit slot supports 264 MBytes/sec.

The multiplexed Address and Data bus allows a reduced pin count on the PCI connector that enables lower cost and smaller package size for PCI components. Typical 32-bit PCI add-in boards use only about 50 signals pins on the PCI connector of which 32 are the multiplexed Address and Data bus. PCI bus cycles are initiated by driving an address onto the AD[31:0] signals during the first clock edge called the address phase. The address phase is signaled by the activation of the FRAME# signal. The next clock edge begins the first of one or more data phases in which data is transferred over the AD[31:0] signals.

In PCI terminology, data is transferred between an initiator which is the bus master, and a target which is the bus slave. The initiator drives the C/BE[3:0]# signals during the address phase to signal the type of transfer (memory read, memory write, I/O read, I/O write, etc.). During data phases the C/BE[3:0]# signals serve as byte enable to indicate which data bytes are valid. Both the initiator and target may insert wait states into the data transfer by deasserting the IRDY# and TRDY# signals. Valid data transfers occur on each clock edge in which both IRDY# and TRDY# are asserted.

A PCI bus transfer consists of one address phase and any number of data phases. I/O operations that access registers within PCI targets typically have only a single data phase. Memory transfers that move blocks of data consist of multiple data phases that read or write multiple consecutive memory locations. Both the initiator and target may terminate a bus transfer sequence at any time. The initiator signals completion of the bus transfer by deasserting the FRAME# signal during the last data phase. A target may terminate a bus transfer by asserting the STOP# signal. When the initiator detects an active STOP# signal, it must terminate the current bus transfer and re-arbitrate for the bus before continuing. If STOP# is asserted without any data phases completing, the target has issued a retry. If STOP# is asserted after one or more data phases have successfully completed, the target has issued a disconnect.

Initiators arbitrate for ownership of the bus by asserting a REQ# signal to a central arbiter. The arbiter grants ownership of the bus by asserting the GNT# signal. REQ# and GNT# are unique on a per slot basis allowing the arbiter to implement a bus fairness algorithm. Arbitration in PCI is “hidden” in the sense that it does not consume clock cycles. The current initiator’s bus transfers are overlapped with the arbitration process that determines the next owner of the bus.

PCI supports a rigorous auto configuration mechanism. Each PCI device includes a set of configuration registers that allow identification of the type of device (SCSI, video, Ethernet, etc.) and the company that produced it. Other registers allow configuration of the device’s I/O addresses, memory addresses, interrupt levels, etc.

Although it is not widely implemented, PCI supports 64-bit addressing. Unlike the 64-bit data bus option which requires a longer connector with additional 32-bits of data signals, 64-bit addressing can be supported through the base 32-bit connector. Dual Address Cycles are issued in which the low order 32-bits of the address are driven onto the AD[31:0] signals during the first address phase, and the high order 32-bits of the address (if non-zero) are driven onto the AD[31:0] signals during a second address phase. The remainder of the transfer continues like a normal bus transfer.

PCI defines support for both 5 Volt and 3.3 Volt signaling levels. The PCI connector defines pin locations for both the 5 Volt and 3.3 Volt levels. However, most early PCI systems were 5 Volt only, and did not provide active power on the 3.3 Volt connector pins. Over time more use of the 3.3 Volt interface is expected, but add-in boards which must work in older legacy systems are restricted to using only the 5 Volt supply. A “keying” scheme is implemented in the PCI connectors to prevent inserting an add-in board into a system with incompatible supply voltage.

Although used most extensively in PC compatible systems, the PCI bus architecture is processor independent. PCI signal definitions are generic allowing the bus to be used in systems based on other processor families. PCI includes strict specifications to ensure the signal quality required for operation at 33 and 66 MHz. Components and add-in boards must include unique bus drivers that are specifically designed for use in a PCI bus environment. Typical TTL devices used in previous bus implementations such as ISA and EISA are not compliant with the requirements of PCI. This restriction along with the high bus speed dictates that most PCI devices are implemented as custom ASICs.

The higher speed of PCI limits the number of expansion slots on a single bus to no more than 3 or 4, as compared to 6 or 7 for earlier bus architectures. To permit expansion buses with more than 3 or 4 slots, the PCI SIG has defined a PCI-to-PCI Bridge mechanism. PCI-to-PCI Bridges are ASICs that electrically isolate two PCI buses while allowing bus transfers to be forwarded from one bus to another. Each bridge device has a “primary” PCI bus and a “secondary” PCI bus. Multiple bridge devices may be cascaded to create a system with many PCI buses.

Chapters:

1. Introduction to PCI protocol
2. PCI Signal Descriptions
3. PCI Bus Transactions
4. PCI Bus Timing Diagrams
5. Configuration space decoding
6. Arbitration process under PCI
7. Error Detection and Reporting

Bibliography

1. PCI Tutorial by Xilinx
2. PCI Bus Demystified by Doug Abbott

Submitted by: Rovin and Sagar

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