Design and verify full adder by using dataflow style with select statement

PROGRAM:

Library ieee;
use ieee.std_logic_1164.all; 
entity fa_select1 is
port(a,b,c:in bit; 
sum,carry:out bit); 
end fa_select1;
architecture df of fa_select1 is begin
with bit_vector'(a,b,c) select (sum,carry)<=bit_vector'("00") when "000" , bit_vector'("10") when "001",
bit_vector'("10") when "010",
bit_vector'("10") when "100",
bit_vector'("01") when "110",
bit_vector'("01") when "011",
bit_vector'("01" )when "101",
bit_vector'("11") when "111"; end df;

SIMULATION OUTPUT:

RESULT: Full adder is simulated and verified

The post Verilog program for Full Adder using dataflow style with select statement first appeared on Student Projects.

Design and verify full subtractor by using dataflow style with select statement.

PROGRAM:

library ieee;
use ieee.std_logic_1164.all; 
entity flsub_select is
port(a:in bit_vector(2 downto 0); 
s:out bit_vector(1 downto 0)); 
end flsub_select;
architecture beh of flsub_select is begin
with a select
s<=("00") when "000",
("11") when "001",
("11") when "010",
("01") when "011",
("10") when "100",
("00") when "101",
("00") when "110",
("11") when "111";
end beh; 

SIMULATION OUTPUT:

RESULT: Full subtractor using dataflow style with select statement is simulated and verified.

The post Verilog program for Full Subtractor by using a behavioral model with if,elsif& then statements. first appeared on Student Projects.

Design and verify full adder by using dataflow style with select statement.

PROGRAM:

Library ieee;
use ieee.std_logic_1164.all; entity fa_select is
port(a:in bit_vector(2 downto 0); 
s:out bit_vector(1 downto 0)); end fa_select ;
architecture beh of fa_select is begin
with a select
s<=("00")when"000",
("10")when"001",
("10")when"010",
("01")when"011",
("10")when"100",
("01")when"101",
("01")when"110",
("11")when"111";
end beh; 

SIMULATION OUTPUT:

RESULT: Full adder using dataflow style with select statement is simulated and Verified.

The post Verilog program for Full Adder by using dataflow style with select statement first appeared on Student Projects.

module primenum3(o,i);
    output o; input [10:0]i; integer k; reg o;
    always @(i)
    begin
    k=i;
    if(i[0]==1'b0)
       begin   o=1'b0; $display("not prime");  end
       else 
       begin
       if(k==3 | k==5 | k==7 | k==11 | k==13 | k==17 | k==19)
       begin  o=1'b1; $display("prime"); end
       else if(k%3==0 | k%5==0 | k%7==0 | k%11==0 | k%13==0 | k%17==0 | k%19==0)
       begin   o=1'b0;  $display("not prime");    end 
       else
       begin   o=1'b1;  $display("prime");        end
       end
        if(i==10'b00 | i==10'b010)
        begin o=1'b1; $display("prime");  end
     end
 endmodule

The post Verilog HDL Program for detecting whether a given number is Prime or not first appeared on Student Projects.

module tff(q,t,c);
    output q;
    input t,c;
    reg q;
    initial 
     begin 
      q=1'b1;
     end
    always @ (posedge c)
    begin
        if (t==1'b0) begin q=q; end
        else begin q=~q;  end
    end
endmodule

module tff1(q,t,c);
    output q;
    input t,c;
    reg q;
    initial 
     begin 
      q=1'b0;
     end
    always @ (posedge c)
    begin
        if (t==1'b0) begin q=q; end
        else begin q=~q;  end
    end
endmodule

module random(o,clk);
    output [3:0]o;      input clk;
    xor (t0,o[3],o[2]);
    assign t1=o[0];
    assign t2=o[1];
    assign t3=o[2];
    tff u1(o[0],t0,clk);
    tff1 u2(o[1],t1,clk);
    tff1 u3(o[2],t2,clk);
    tff1 u4(o[3],t3,clk);
endmodule

The post Verilog HDL Program for Random Number Generator first appeared on Student Projects.

module sftsum(f,x);
    output [3:0]f;
    input [3:0]x;
    reg [3:0]f;
    reg [3:0]a,b;
    always @ (x)
    begin
        a=x>>3;
        b=x<<4;
        f=a+b;
    end
endmodule

The post Verilog HDL Program for the function f=x>>3 + x<<4 first appeared on Student Projects.

module carrysave(s,c,a,b);
    output [3:0]s;
    output c;
    input [3:0]a,b;
    wire [2:0]c2,c0;
    fa u1(s[0],c0[0],a[0],b[0],1'b0);
    dff1 u2(c2[0],c0[0],clk);
    fa u3(s[1],c0[1],a[1],b[1],c2[0]);
    dff1 u4(c2[1],c0[1],clk);
    fa u5(s[2],c0[2],a[2],b[2],c2[1]);
    dff1 u6(c2[2],c0[2],clk);
    fa u7(s[3],c,a[3],b[3],c2[2]);
endmodule

The post Verilog HDL Program for Carry Save Adder first appeared on Student Projects.

module count1(o1,o0,i); // 4-bit vector
    output [2:0]o1,o0; // o1: Number of 1’s in vector, o0: Number of 0’s in vector
    input [3:0]i;    wire [2:0]o;    wire [3:1]c;
    ha u1(o[0],c0,i[0],i[1]);
    ha u2(o[1],c1,o[0],i[2]);
    ha u3(o[2],c2,o[1],i[3]);
    ha u4(c[1],c3,c1,c0);
    ha u5(c[2],c[3],c[1],c2);
    assign o1={c[3],c[2],o[2]};
    pasub31 u6(o0,3'b100,o1);
endmodule

module pasub31(d,a,b);//a-b
    output [2:0]d;     input [2:0]a;     input [2:0]b;
    hs u1(d[0],c1,a[0],b[0]);
    fs u2(d[1],c2,a[1],b[1],c1);
    fs u3(d[2],c,a[2],b[2],c2);
endmodule

The post Verilog HDL Program for Counting Number of 1’s in a Vector first appeared on Student Projects.

module spm(s,m,q);
    output [7:0]s;
    input [3:0]m,q;
    and1 u1(s[0],m[0],q[0]);
    and1 u2(s1,m[0],q[1]);
    and1 u3(s2,m[0],q[2]);
    and1 u4(s3,m[0],q[3]);
    and1 u5(s4,m[1],q[0]);
    and1 u6(s5,m[1],q[1]);
    and1 u7(s6,m[1],q[2]);
    and1 u8(s7,m[1],q[3]);
    and1 u9(s8,m[2],q[0]);
    and1 u10(s9,m[2],q[1]);
    and1 u11(s10,m[2],q[2]);
    and1 u12(s11,m[2],q[3]);
    and1 u13(s12,m[3],q[0]);
    and1 u14(s13,m[3],q[1]);
    and1 u15(s14,m[3],q[2]);
    and1 u16(s15,m[3],q[3]);
    parad4 u21({s18,s17,s16,s[1]},c3,{s7,s6,s5,s4},{1'b0,s3,s2,s1});
    parad4 u22({s21,s20,s19,s[2]},c7,{c3,s18,s17,s16},{s11,s10,s9,s8});
    parad4 u23({s[6],s[5],s[4],s[3]},s[7],{c7,s21,s20,s19},{s15,s14,s13,s12});
endmodule

module parad4(a,c,p,q); // Parallel Adder Module
    output [3:0]a;     output c;     input [3:0]p,q;    wire c1,c2,c3;
    ha u1(a[0],c1,p[0],q[0]);
    fa u2(a[1],c2,p[1],q[1],c1);
    fa u3(a[2],c3,p[2],q[2],c2);
    fa u4(a[3],c,p[3],q[3],c3);
endmodule

The post Verilog HDL Program for Serial Parallel Multiplier first appeared on Student Projects.

module mod10(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1(qc,q3);
    inv u2(qb,q1);
    inv u3(qa,q0);
    and1 u4(j3,q1,q0,q2);
    assign k3=q0;
    and1 u5(k2,q1,q0);
    assign j2=k2;
    and1 u6(j1,qc,q0);
    assign k1=q0;
    assign j0=1'b1;
    assign k0=1'b1;
    jk1 u11(qo[0],j0,k0,clk);
    jk1 u12(qo[1],j1,k1,clk);
    jk1 u13(qo[2],j2,k2,clk);
    jk1 u14(qo[3],j3,k3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule

The post Verilog HDL Program for Decade Counter first appeared on Student Projects.