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		<title>Verilog HDL Program for EXCLUSIVE OR Logic Gate</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-exclusive-or-logic-gate/</link>
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		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Thu, 31 May 2012 13:48:36 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[xor gate]]></category>
		<category><![CDATA[verilog]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=2991</guid>

					<description><![CDATA[<p>The XOR gate is a digital logic gate that implements an exclusive or; that is, a true output (1) results if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) or both are true (1), a false output (0) results. A way to remember XOR</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-exclusive-or-logic-gate/">Verilog HDL Program for EXCLUSIVE OR Logic Gate</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>The XOR gate is a digital logic gate that implements an exclusive or; that is, a true output (1) results if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) or both are true (1), a false output (0) results. A way to remember XOR is &#8220;one or the other but not both&#8221;. It represents the inequality function, i.e., the output is HIGH (1) if the inputs are not alike otherwise the output is LOW (0).</p>
<p>This Function is addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A half adder consists of an XOR gate and an AND gate.</p>
<pre lang="VHDL" line="1">
module xor1(c,a,b);
    output c;
    input a,b;
    wire d,e,f,g;
    inv u1(d,a);
    inv u2(e,b);
    and1 u3(f,a,e);
    and1 u4(g,b,d);
    or1 u5(c,f,g);
endmodule
</pre>
<figure id="attachment_2992" aria-describedby="caption-attachment-2992" style="width: 614px" class="wp-caption aligncenter"><img decoding="async" src="https://studentprojects.in/wp-content/uploads/2012/05/Simulated-waveform-for-Ex-or-Gate.jpg" alt="Simulated waveform for Ex-or Gate" title="Simulated waveform for Ex-or Gate" width="614" height="160" class="size-full wp-image-2992" /><figcaption id="caption-attachment-2992" class="wp-caption-text">Simulated waveform for Ex-or Gate</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-exclusive-or-logic-gate/">Verilog HDL Program for EXCLUSIVE OR Logic Gate</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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