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	<title>xnor gate | Student Projects</title>
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		<title>Verilog HDL Program for EXCLUSIVE NOR Logic Gate</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-exclusive-nor-logic-gate/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-exclusive-nor-logic-gate/#respond</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Thu, 31 May 2012 13:52:17 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[xnor gate]]></category>
		<category><![CDATA[verilog]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=2995</guid>

					<description><![CDATA[<p>The XNOR gate is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. A HIGH output (1) results if both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW output (0) results. module xnor1(c,a,b); output c; input a,b;</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-exclusive-nor-logic-gate/">Verilog HDL Program for EXCLUSIVE NOR Logic Gate</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>The XNOR gate is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. A HIGH output (1) results if both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW output (0) results.</p>
<pre lang="VHDL" line="1">
module xnor1(c,a,b);
    output c;
    input a,b;
    wire d,e,f,g;
    inv u1(d,a);
    inv u2(e,b);
    and1 u3(f,a,b);
    and1 u4(g,e,d);
    or1 u5(c,f,g);
endmodule
</pre>
<figure id="attachment_2996" aria-describedby="caption-attachment-2996" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" src="https://studentprojects.in/wp-content/uploads/2012/05/Simulated-waveform-for-Ex-nor-Gate.jpg" alt="Simulated waveform for Ex-nor Gate" title="Simulated waveform for Ex-nor Gate" width="615" height="159" class="size-full wp-image-2996" /><figcaption id="caption-attachment-2996" class="wp-caption-text">Simulated waveform for Ex-nor Gate</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-exclusive-nor-logic-gate/">Verilog HDL Program for EXCLUSIVE NOR Logic Gate</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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