module carrysave(s,c,a,b);
    output [3:0]s;
    output c;
    input [3:0]a,b;
    wire [2:0]c2,c0;
    fa u1(s[0],c0[0],a[0],b[0],1'b0);
    dff1 u2(c2[0],c0[0],clk);
    fa u3(s[1],c0[1],a[1],b[1],c2[0]);
    dff1 u4(c2[1],c0[1],clk);
    fa u5(s[2],c0[2],a[2],b[2],c2[1]);
    dff1 u6(c2[2],c0[2],clk);
    fa u7(s[3],c,a[3],b[3],c2[2]);
endmodule

The post Verilog HDL Program for Carry Save Adder first appeared on Student Projects.

 
module sipo(sout,sin,clk);
    output [3:0]sout;
    input sin,clk;
    dff2 u1(sout[0],sin,clk);
    dff2 u2(sout[1],sout[0],clk);
    dff2 u3(sout[2],sout[1],clk);
    dff2 u4(sout[3],sout[2],clk);
endmodule

The post Verilog HDL Program for Serail In – Parallel Out Shift Register first appeared on Student Projects.

module pipo(sout,sin,clk);
    output [3:0]sout;
    input [3:0]sin;
    input clk;
    dff1 u1(sout[0],sin[0],clk);
    dff1 u2(sout[1],sin[1],clk);
    dff1 u3(sout[2],sin[2],clk);
    dff1 u4(sout[3],sin[3],clk);
endmodule

The post Verilog HDL Program for Parallel In – Parallel Out Shift Register first appeared on Student Projects.

module piso1(sout,sin,clk);
    output sout;
    input [3:0]sin;
    input clk;
    wire [3:0]q;
    inv u1(p,sl);
    and1 u2(n,sin[1],p);
    and1 u3(r,sl,q[0]);
    or1 u4(s,n,r);
    and1 u5(t,sin[2],p);
    and1 u6(u,sl,q[1]);
    or1 u7(v,u,t);
    and1 u8(w,sin[3],p);
    and1 u9(y,sl,q[2]);
    or1 u10(z,w,y);
    dff1 u11(q[0],sin[0],clk);
    dff1 u12(q[1],s,clk);
    dff1 u13(q[2],v,clk);
    dff1 u14(q[3],z,clk);
    assign sout = q[3];
endmodule

The post Verilog HDL Program for Parallel In – Serial Out Shift Register first appeared on Student Projects.

module bcd2gray(o,i);
    output [2:0]o;
    input [2:0]i;
    reg [2:0]o;
    always @(i)
    begin
        o[2]=i[2];
        o[1]=i[2]^i[1];
        o[0]=i[1]^i[0];
    end
endmodule

The post Verilog HDL Program for BCD to GRAY conversion first appeared on Student Projects.

module sr2d(q,q1,d,clk);
output q,q1;
input d,clk;
wire x;
inv u1(x,d);
srff u2(q,q1,x,d,clk); //srff u(q,q1,r,s,clk);
endmodule

The post Verilog HDL Program for D flip flop using RS flip flop first appeared on Student Projects.

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a “flip” or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop.

module jk(q,q1,j,k,c);
output q,q1;
input j,k,c;
reg q,q1;
initial begin q=1'b0; q1=1'b1; end
always @ (posedge c)
  begin
	case({j,k})
		 {1'b0,1'b0}:begin q=q; q1=q1; end
		 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
		 {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
		 {1'b1,1'b1}: begin q=~q; q1=~q1; end
	endcase
   end
endmodule  

The post Verilog HDL Program for J K Flip Flop first appeared on Student Projects.

module encoder83(o,i);
    output [2:0]o;
    input [7:0]i;
    wire x,y,k,l,m;
    or1 u1(x,i[5],i[4]);
    or1 u2(y,i[7],i[6]);
    or1 u3(o[2],x,y);
    or1 u4(k,i[3],i[2]);
    or1 u5(o[1],y,k);
    or1 u6(l,i[7],i[5]);
    or1 u7(m,i[3],i[1]);
    or1 u8(o[0],l,m);
endmodule

The post Verilog HDL Program for 3-8 ENCODER first appeared on Student Projects.

module xnor1(c,a,b);
    output c;
    input a,b;
    wire d,e,f,g;
    inv u1(d,a);
    inv u2(e,b);
    and1 u3(f,a,b);
    and1 u4(g,e,d);
    or1 u5(c,f,g);
endmodule

The post Verilog HDL Program for EXCLUSIVE NOR Logic Gate first appeared on Student Projects.

This Function is addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A half adder consists of an XOR gate and an AND gate.

module xor1(c,a,b);
    output c;
    input a,b;
    wire d,e,f,g;
    inv u1(d,a);
    inv u2(e,b);
    and1 u3(f,a,e);
    and1 u4(g,b,d);
    or1 u5(c,f,g);
endmodule

The post Verilog HDL Program for EXCLUSIVE OR Logic Gate first appeared on Student Projects.