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		<title>Verilog HDL Program for detecting whether a given number is Prime or not</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-detecting-whether-a-given-number-is-prime-or-not/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-detecting-whether-a-given-number-is-prime-or-not/#respond</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 10:06:14 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[vlsi]]></category>
		<category><![CDATA[prime number]]></category>
		<category><![CDATA[verilog pragram]]></category>
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					<description><![CDATA[<p>Verilog HDL Program for detecting whether a given number is Prime or not. module primenum3(o,i); output o; input [10:0]i; integer k; reg o; always @(i) begin k=i; if(i[0]==1'b0) begin o=1'b0; $display("not prime"); end else begin if(k==3 &#124; k==5 &#124; k==7 &#124; k==11 &#124; k==13 &#124; k==17 &#124; k==19) begin o=1'b1; $display("prime"); end else if(k%3==0 &#124;</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-detecting-whether-a-given-number-is-prime-or-not/">Verilog HDL Program for detecting whether a given number is Prime or not</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>Verilog HDL Program for detecting whether a given number is Prime or not.</p>
<pre lang="Verilog" line="1">
module primenum3(o,i);
    output o; input [10:0]i; integer k; reg o;
    always @(i)
    begin
    k=i;
    if(i[0]==1'b0)
       begin   o=1'b0; $display("not prime");  end
       else 
       begin
       if(k==3 | k==5 | k==7 | k==11 | k==13 | k==17 | k==19)
       begin  o=1'b1; $display("prime"); end
       else if(k%3==0 | k%5==0 | k%7==0 | k%11==0 | k%13==0 | k%17==0 | k%19==0)
       begin   o=1'b0;  $display("not prime");    end 
       else
       begin   o=1'b1;  $display("prime");        end
       end
        if(i==10'b00 | i==10'b010)
        begin o=1'b1; $display("prime");  end
     end
 endmodule
</pre>
<figure id="attachment_3276" aria-describedby="caption-attachment-3276" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-waveform-for-detecting-whether-a-given-number-is-Prime-or-not.jpg" alt="Simulated waveform for detecting whether a given number is Prime or not" title="Simulated waveform for detecting whether a given number is Prime or not" width="615" height="33" class="size-full wp-image-3276" /><figcaption id="caption-attachment-3276" class="wp-caption-text">Simulated waveform for detecting whether a given number is Prime or not</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-detecting-whether-a-given-number-is-prime-or-not/">Verilog HDL Program for detecting whether a given number is Prime or not</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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