module sr2jk(q,q1,j,k,clk);
	output q,q1;
	input j,k,clk;
	and1 u1(w,j,q1);
	inv u4(k1,k);
	and1 u2(x,k1,q);
	srff u3(q,q1,x,w,clk);
	endmodule

The post Verilog HDL Program for JK flip flop using RS flip flop first appeared on Student Projects.

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

module srff(q,q1,r,s,clk);
	output q,q1;
	input r,s,clk;
	reg q,q1;
	initial
	begin
		q=1'b0;
		q1=1'b1;
	end
	always @(posedge clk)
	  begin
	  case({s,r})
		 {1'b0,1'b0}: begin q=q; q1=q1; end
		 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
		 {1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
		 {1'b1,1'b1}: begin q=1'bx; q=1'bx; end
	endcase
	end
endmodule

The post Verilog HDL Program for R-S Flip Flops first appeared on Student Projects.