Verilog lab programs | Student Projects

Verilog HDL Program for Serial Parallel Multiplier

Ansten Lobo — Sat, 09 Jun 2012 09:55:17 +0000

Verilog HDL Program for Serial Parallel Multiplier.

module spm(s,m,q);
    output [7:0]s;
    input [3:0]m,q;
    and1 u1(s[0],m[0],q[0]);
    and1 u2(s1,m[0],q[1]);
    and1 u3(s2,m[0],q[2]);
    and1 u4(s3,m[0],q[3]);
    and1 u5(s4,m[1],q[0]);
    and1 u6(s5,m[1],q[1]);
    and1 u7(s6,m[1],q[2]);
    and1 u8(s7,m[1],q[3]);
    and1 u9(s8,m[2],q[0]);
    and1 u10(s9,m[2],q[1]);
    and1 u11(s10,m[2],q[2]);
    and1 u12(s11,m[2],q[3]);
    and1 u13(s12,m[3],q[0]);
    and1 u14(s13,m[3],q[1]);
    and1 u15(s14,m[3],q[2]);
    and1 u16(s15,m[3],q[3]);
    parad4 u21({s18,s17,s16,s[1]},c3,{s7,s6,s5,s4},{1'b0,s3,s2,s1});
    parad4 u22({s21,s20,s19,s[2]},c7,{c3,s18,s17,s16},{s11,s10,s9,s8});
    parad4 u23({s[6],s[5],s[4],s[3]},s[7],{c7,s21,s20,s19},{s15,s14,s13,s12});
endmodule

module parad4(a,c,p,q); // Parallel Adder Module
    output [3:0]a;     output c;     input [3:0]p,q;    wire c1,c2,c3;
    ha u1(a[0],c1,p[0],q[0]);
    fa u2(a[1],c2,p[1],q[1],c1);
    fa u3(a[2],c3,p[2],q[2],c2);
    fa u4(a[3],c,p[3],q[3],c3);
endmodule

Simulated waveform for Serial Parallel Multiplier

The post Verilog HDL Program for Serial Parallel Multiplier first appeared on Student Projects.

Verilog HDL Program for J K Flip Flop

Ansten Lobo — Sat, 09 Jun 2012 06:36:29 +0000

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a “flip” or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop.

module jk(q,q1,j,k,c);
output q,q1;
input j,k,c;
reg q,q1;
initial begin q=1'b0; q1=1'b1; end
always @ (posedge c)
  begin
	case({j,k})
		 {1'b0,1'b0}:begin q=q; q1=q1; end
		 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
		 {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
		 {1'b1,1'b1}: begin q=~q; q1=~q1; end
	endcase
   end
endmodule

Simulated waveform for J-K Flip Flop

The post Verilog HDL Program for J K Flip Flop first appeared on Student Projects.

Verilog HDL program for 2 – 4 Decoder

Ansten Lobo — Sat, 02 Jun 2012 09:37:19 +0000

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.

module decoder24(c,a,b,e);
    output [3:0]c;
    input a,b,e;
    wire x,y;
    wire [3:0]c1;
    inv u1(x,a);
    inv u2(y,b);
    and1 u3(c1[0],x,y);
    and1 u4(c1[1],x,b);
    and1 u5(c1[2],a,y);
    and1 u6(c1[3],a,b);
    and1 u7(c[0],c1[0],e);
    and1 u8(c[1],c1[1],e);
    and1 u9(c[2],c1[2],e);
    and1 u10(c[3],c1[3],e);
endmodule

Simulated waveform for 2-4 Decoder

The post Verilog HDL program for 2 – 4 Decoder first appeared on Student Projects.