module sr2t(q,q1,t,clk);
output q,q1;
input t,clk;
wire x,y;
and1 u1(x,t,q1);
and1 u2(y,t,q);
srff u3(q,q1,y,x,clk); //srff u(q,q1,r,s,clk);
endmodule

The post Verilog HDL Program for T flip flop using RS flip flop first appeared on Student Projects.

	module sr2jk(q,q1,j,k,clk);
	output q,q1;
	input j,k,clk;
	and1 u1(w,j,q1);
	inv u4(k1,k);
	and1 u2(x,k1,q);
	srff u3(q,q1,x,w,clk);
	endmodule

The post Verilog HDL Program for JK flip flop using RS flip flop first appeared on Student Projects.