module dff(q,d,c);
    output q;
    input d,c;
    reg q;
    initial   
     q=1'b1; 
    always @ (posedge c)
       q=d;
    endmodule

module dff1(q,d,clk);
    output q;
    input d,clk;
    reg q;
    initial 
    q=1'b0;
    always @ (posedge clk)
    q=d;
endmodule

module ring(q,clk);
    inout [3:0]q;
    input clk;
    dff u1(q[0],q[3],clk);
    dff1 u2(q[1],q[0],clk);
    dff1 u3(q[2],q[1],clk);
    dff1 u4(q[3],q[2],clk);
endmodule

The post Verilog HDL Program for Ring Counter first appeared on Student Projects.