Parallel In – Parallel Out | Student Projects https://studentprojects.in Microcontroller projects, Circuit Diagrams, Project Ideas Sat, 09 Jun 2012 09:39:51 +0000 en-US hourly 1 https://wordpress.org/?v=6.1.7 Verilog HDL Program for Parallel In – Parallel Out Shift Register https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-parallel-in-parallel-out-shift-register/ https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-parallel-in-parallel-out-shift-register/#comments Sat, 09 Jun 2012 09:39:51 +0000 http://studentprojects.in/?p=3240 Verilog HDL Program for Parallel In – Parallel Out Shift Register module pipo(sout,sin,clk); output [3:0]sout; input [3:0]sin; input clk; dff1 u1(sout[0],sin[0],clk); dff1 u2(sout[1],sin[1],clk); dff1 u3(sout[2],sin[2],clk); dff1 u4(sout[3],sin[3],clk); endmodule

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]]> Verilog HDL Program for Parallel In – Parallel Out Shift Register

module pipo(sout,sin,clk);
    output [3:0]sout;
    input [3:0]sin;
    input clk;
    dff1 u1(sout[0],sin[0],clk);
    dff1 u2(sout[1],sin[1],clk);
    dff1 u3(sout[2],sin[2],clk);
    dff1 u4(sout[3],sin[3],clk);
endmodule
Simulated Waveform for Parallel In – Parallel Out Shift Register
Simulated Waveform for Parallel In – Parallel Out Shift Register

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