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	<title>Multiplexer | Student Projects</title>
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		<title>Verilog HDL Program for 2X1 Multiplexer</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2x1-multiplexer/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2x1-multiplexer/#respond</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 04:47:10 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[vhdl program]]></category>
		<category><![CDATA[Multiplexer]]></category>
		<category><![CDATA[2X1 Multiplexer]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3168</guid>

					<description><![CDATA[<p>a multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2x1-multiplexer/">Verilog HDL Program for 2X1 Multiplexer</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>a multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector. They are used in CCTV, and almost every business that has CCTV fitted, will own one of these.</p>
<pre lang="ASM" line="1">
module mux211(q,i1,i0,s);
    output q;
    input i1,i0,s;
    not (u,s);
    and (m,s,i1);
    and (n,u,i0);
    or (q,m,n);
endmodule
</pre>
<figure id="attachment_3169" aria-describedby="caption-attachment-3169" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-waveform-for-2-X-1-Multiplexer.jpg" alt="Simulated waveform for 2 X 1 Multiplexer" title="Simulated waveform for 2 X 1 Multiplexer" width="615" height="115" class="size-full wp-image-3169" /><figcaption id="caption-attachment-3169" class="wp-caption-text">Simulated waveform for 2 X 1 Multiplexer</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2x1-multiplexer/">Verilog HDL Program for 2X1 Multiplexer</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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