module mod13(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1 (qd,q3);
    inv u2(qc,q2);
    and1 u3 (a,q1,q0,q2);
    and1 u4(b,q3,q2);
    or1 u5(t3,a,b);
    and1 u6(c,q1,q0);
    and1 u7(d,q3,q2);
    or1 u8(t2,c,d);
    assign t1=q0;
    or1 u9(t0,qd,qc);
    tff u10(qo[0],t0,clk);
    tff u12(qo[1],t1,clk);
    tff u13(qo[2],t2,clk);
    tff u14(qo[3],t3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule

The post Verilog HDL Program for Mod-13 Counter first appeared on Student Projects.