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	<title>lab programs | Student Projects</title>
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	<description>Microcontroller projects, Circuit Diagrams, Project Ideas</description>
	<lastBuildDate>Sat, 09 Jun 2012 16:38:56 +0000</lastBuildDate>
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	<item>
		<title>C Program for Simple/Linear QUEUE Operations – Using Array</title>
		<link>https://studentprojects.in/software-development/c-tutorials/c/data-structures-c/c-program-for-simple-linear-queue-operations-using-array/</link>
					<comments>https://studentprojects.in/software-development/c-tutorials/c/data-structures-c/c-program-for-simple-linear-queue-operations-using-array/#comments</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 16:38:32 +0000</pubDate>
				<category><![CDATA[Data Structures]]></category>
		<category><![CDATA[c program]]></category>
		<category><![CDATA[queue operations]]></category>
		<category><![CDATA[using array]]></category>
		<category><![CDATA[lab programs]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3303</guid>

					<description><![CDATA[<p>Source: Dr. G T Raju, Professor &#038; Head, Dept. of CSE, RNSIT #define SIZE 5 /* Size of Queue */ int Q[SIZE],f=0,r=-1; /* Global declarations */ Qinsert(int elem) { /* Function for Insert operation */ if( Qfull()) printf("\n\n Overflow!!!!\n\n"); else { ++r; Q[r]=elem; } } int Qdelete() { /* Function for Delete operation */ int</p>
<p>The post <a href="https://studentprojects.in/software-development/c-tutorials/c/data-structures-c/c-program-for-simple-linear-queue-operations-using-array/">C Program for Simple/Linear QUEUE Operations – Using Array</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>Source: Dr. G T Raju, Professor &#038; Head, Dept. of CSE, RNSIT</p>
<pre lang="C" line="1">
#define SIZE 5            /* Size of Queue */
int Q[SIZE],f=0,r=-1;       /* Global declarations */

Qinsert(int elem)
{                       /* Function for Insert operation */
    if( Qfull()) printf("\n\n Overflow!!!!\n\n");
    else
    {
        ++r;
        Q[r]=elem;
    }
}

int Qdelete()
{                      /* Function for Delete operation */
    int elem;
    if(Qempty()){ printf("\n\nUnderflow!!!!\n\n");
    return(-1); }
    else
    {
        elem=Q[f];
        f=f+1;
        return(elem);
    }
}

int Qfull()
{                     /* Function to Check Queue Full */
    if(r==SIZE-1) return 1;
    return 0;
}

int Qempty()
{                    /* Function to Check Queue Empty */
    if(f > r) return 1;
    return 0;
}

display()
{                  /* Function to display status of Queue */
    int i;
    if(Qempty()) printf(" \n Empty Queue\n");
    else
    {
        printf("Front->");
        for(i=f;i<=r;i++)
            printf("%d ",Q[i]);
        printf("<-Rear");
    }
}

main()
{                         /* Main Program */
    int opn,elem;
    do
    {
        clrscr();
        printf("\n ### Queue Operations ### \n\n");
        printf("\n Press 1-Insert, 2-Delete,3-Display,4-Exit\n");
        printf("\n Your option ? ");
        scanf("%d",&#038;opn);
        switch(opn)
        {
        case 1: printf("\n\nRead the element to be Inserted ?");
            scanf("%d",&#038;elem);
            Qinsert(elem); break;
        case 2: elem=Qdelete();
            if( elem != -1)
                printf("\n\nDeleted Element is %d \n",elem);
            break;
        case 3: printf("\n\nStatus of Queue\n\n");
            display(); break;
        case 4: printf("\n\n Terminating \n\n"); break;
        default: printf("\n\nInvalid Option !!! Try Again !! \n\n");
            break;
        }
        printf("\n\n\n\n  Press a Key to Continue . . . ");
        getch();
    }while(opn != 4);
}
</pre><p>The post <a href="https://studentprojects.in/software-development/c-tutorials/c/data-structures-c/c-program-for-simple-linear-queue-operations-using-array/">C Program for Simple/Linear QUEUE Operations – Using Array</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			<slash:comments>2</slash:comments>
		
		
			</item>
		<item>
		<title>C program to insert Student Records to a Sequential File</title>
		<link>https://studentprojects.in/software-development/c-tutorials/c/c-advanced/c-program-to-insert-student-records-to-a-sequential-file/</link>
					<comments>https://studentprojects.in/software-development/c-tutorials/c/c-advanced/c-program-to-insert-student-records-to-a-sequential-file/#respond</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 11:41:46 +0000</pubDate>
				<category><![CDATA[Advanced programs]]></category>
		<category><![CDATA[insert records]]></category>
		<category><![CDATA[Sequential File]]></category>
		<category><![CDATA[lab programs]]></category>
		<category><![CDATA[c programs]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3288</guid>

					<description><![CDATA[<p>Source: Dr. G T Raju, Professor &#038; Head, Dept. of CSE, RNSIT #include typedef struct { int usn; char name[25]; int m1,m2,m3; }STD; STD s; void display(FILE *); int search(FILE *,int); void main() { int i,n,usn_key,opn; FILE *fp; printf(" How many Records ? "); scanf("%d",&#038;n); fp=fopen("stud.dat","w"); for(i=0;i</p>
<p>The post <a href="https://studentprojects.in/software-development/c-tutorials/c/c-advanced/c-program-to-insert-student-records-to-a-sequential-file/">C program to insert Student Records to a Sequential File</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>Source: Dr. G T Raju, Professor &#038; Head, Dept. of CSE, RNSIT</p>
<pre lang="C" line="1">
#include <stdio.h>
typedef struct
{
    int usn;
    char name[25];
    int m1,m2,m3;
}STD;
STD s;
void display(FILE *);
int search(FILE *,int);
void main()
{
    int i,n,usn_key,opn;
    FILE *fp;
    printf(" How many Records ? ");
    scanf("%d",&n);
    fp=fopen("stud.dat","w");
    for(i=0;i<n;i++)
    {
        printf("Read the Info for Student: %d (usn,name,m1,m2,m3) \n",i+1);
        scanf("%d%s%d%d%d",&#038;s.usn,s.name,&#038;s.m1,&#038;s.m2,&#038;s.m3);
        fwrite(&#038;s,sizeof(s),1,fp);
    }
    fclose(fp);
    fp=fopen("stud.dat","r");
    do
    {
        printf("Press 1- Display\t 2- Search\t 3- Exit\t Your Option?");
        scanf("%d",&#038;opn);
        switch(opn)
        {
        case 1: printf("\n Student Records in the File \n");
            display(fp);
            break;
        case 2: printf(" Read the USN of the student to be searched ?");
            scanf("%d",&#038;usn_key);
            if(search(fp,usn_key))
            {
                printf("Success ! Record found in the file\n");
                printf("%d\t%s\t%d\t%d\t%d\n",s.usn,s.name,s.m1,s.m2,s.m3);
            }
            else
                printf(" Failure!! Record with USN %d not found\n",usn_key);
            break;
        case 3:  printf(" Exit!! Press a key . . .");
            getch();
            break;
        default:  printf(" Invalid Option!!! Try again !!!\n");
            break;
        }
    }while(opn != 3);
    fclose(fp);
}   /* End of main() */
void display(FILE *fp)
{
    rewind(fp);
    while(fread(&#038;s,sizeof(s),1,fp))
        printf("%d\t%s\t%d\t%d\t%d\n",s.usn,s.name,s.m1,s.m2,s.m3);
}
int search(FILE *fp, int usn_key)
{
    rewind(fp);
    while(fread(&#038;s,sizeof(s),1,fp))
        if( s.usn == usn_key) return 1;
    return 0;
}
</pre><p>The post <a href="https://studentprojects.in/software-development/c-tutorials/c/c-advanced/c-program-to-insert-student-records-to-a-sequential-file/">C program to insert Student Records to a Sequential File</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Verilog HDL Program for Decade Counter</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-decade-counter/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-decade-counter/#respond</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 09:52:53 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[lab programs]]></category>
		<category><![CDATA[Verilog programs]]></category>
		<category><![CDATA[HDL]]></category>
		<category><![CDATA[vlsi]]></category>
		<category><![CDATA[Decade Counter]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3256</guid>

					<description><![CDATA[<p>Verilog HDL Program for Decade Counter. module mod10(qo,clk); output [3:0]qo; input clk; inv u1(qc,q3); inv u2(qb,q1); inv u3(qa,q0); and1 u4(j3,q1,q0,q2); assign k3=q0; and1 u5(k2,q1,q0); assign j2=k2; and1 u6(j1,qc,q0); assign k1=q0; assign j0=1'b1; assign k0=1'b1; jk1 u11(qo[0],j0,k0,clk); jk1 u12(qo[1],j1,k1,clk); jk1 u13(qo[2],j2,k2,clk); jk1 u14(qo[3],j3,k3,clk); assign {q3,q2,q1,q0}=qo; endmodule</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-decade-counter/">Verilog HDL Program for Decade Counter</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>Verilog HDL Program for Decade Counter.</p>
<pre lang="Verilog" line="1">
module mod10(qo,clk);
    output [3:0]qo;
    input clk;
    inv u1(qc,q3);
    inv u2(qb,q1);
    inv u3(qa,q0);
    and1 u4(j3,q1,q0,q2);
    assign k3=q0;
    and1 u5(k2,q1,q0);
    assign j2=k2;
    and1 u6(j1,qc,q0);
    assign k1=q0;
    assign j0=1'b1;
    assign k0=1'b1;
    jk1 u11(qo[0],j0,k0,clk);
    jk1 u12(qo[1],j1,k1,clk);
    jk1 u13(qo[2],j2,k2,clk);
    jk1 u14(qo[3],j3,k3,clk);
    assign {q3,q2,q1,q0}=qo;
endmodule
</pre>
<figure id="attachment_3257" aria-describedby="caption-attachment-3257" style="width: 813px" class="wp-caption aligncenter"><img decoding="async" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-Waveform-for-Decade-Counter.jpg" alt="Simulated Waveform for Decade Counter" title="Simulated Waveform for Decade Counter" width="813" height="296" class="size-full wp-image-3257" /><figcaption id="caption-attachment-3257" class="wp-caption-text">Simulated Waveform for Decade Counter</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-decade-counter/">Verilog HDL Program for Decade Counter</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Verilog HDL Program for D flip flop using RS flip flop</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop-using-rs-flip-flop/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop-using-rs-flip-flop/#comments</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 09:23:49 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[verilog]]></category>
		<category><![CDATA[lab programs]]></category>
		<category><![CDATA[HDL]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3224</guid>

					<description><![CDATA[<p>Verilog HDL Program for D flip flop using RS flip flop. module sr2d(q,q1,d,clk); output q,q1; input d,clk; wire x; inv u1(x,d); srff u2(q,q1,x,d,clk); //srff u(q,q1,r,s,clk); endmodule</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop-using-rs-flip-flop/">Verilog HDL Program for D flip flop using RS flip flop</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>Verilog HDL Program for D flip flop using RS flip flop.</p>
<pre lang="Verilog" line="1">
module sr2d(q,q1,d,clk);
output q,q1;
input d,clk;
wire x;
inv u1(x,d);
srff u2(q,q1,x,d,clk); //srff u(q,q1,r,s,clk);
endmodule
</pre>
<figure id="attachment_3225" aria-describedby="caption-attachment-3225" style="width: 553px" class="wp-caption aligncenter"><img decoding="async" loading="lazy" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-Waveform-for-D-flip-flop-using-RS-flip-flop.jpg" alt="Simulated Waveform for D flip flop using RS flip flop" title="Simulated Waveform for D flip flop using RS flip flop" width="553" height="98" class="size-full wp-image-3225" /><figcaption id="caption-attachment-3225" class="wp-caption-text">Simulated Waveform for D flip flop using RS flip flop</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop-using-rs-flip-flop/">Verilog HDL Program for D flip flop using RS flip flop</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Verilog HDL Program for T Flip Flop</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-t-flip-flop/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-t-flip-flop/#respond</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 07:50:54 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[lab programs]]></category>
		<category><![CDATA[T Flip Flop]]></category>
		<category><![CDATA[Verilog programs]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3186</guid>

					<description><![CDATA[<p>A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-t-flip-flop/">Verilog HDL Program for T Flip Flop</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.</p>
<p>If the T input is high, the T flip-flop changes state (&#8220;toggles&#8221;) whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value.</p>
<pre lang="VHDL" line="1">
module t(q,q1,t,c);
output q,q1;
input t,c;
reg q,q1;
initial 
   begin 
	q=1'b1;
	q1=1'b0;
   end
 always @ (c)
	begin
		if(c)
			 begin
			   if (t==1'b0) begin q=q; q1=q1; end
			   else begin q=~q; q1=~q1; end
			 end
	 end
endmodule    
</pre>
<figure id="attachment_3187" aria-describedby="caption-attachment-3187" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" loading="lazy" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-Wave-form-for-Toggle-flip-flop.jpg" alt="Simulated Wave form for Toggle flip flop" title="Simulated Wave form for Toggle flip flop" width="615" height="79" class="size-full wp-image-3187" /><figcaption id="caption-attachment-3187" class="wp-caption-text">Simulated Wave form for Toggle flip flop</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-t-flip-flop/">Verilog HDL Program for T Flip Flop</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Verilog HDL Program for D Flip Flop</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop/#comments</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 06:44:59 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[D Flip Flop]]></category>
		<category><![CDATA[Verilog programs]]></category>
		<category><![CDATA[lab programs]]></category>
		<category><![CDATA[Source Codes]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3183</guid>

					<description><![CDATA[<p>A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop/">Verilog HDL Program for D Flip Flop</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.</p>
<p>he D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.</p>
<pre lang="VHDL" line="1">
module d(q,q1,d,c);
output q,q1;
 input d,c;
 reg q,q1;
	initial 
	   begin
		   q=1'b0; q1=1'b1;
	  end
	always @ (posedge c)
	   begin 
		 q=d;
		 q1= ~d;
	   end
endmodule
</pre>
<figure id="attachment_3184" aria-describedby="caption-attachment-3184" style="width: 564px" class="wp-caption aligncenter"><img decoding="async" loading="lazy" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-waveform-for-D-Flip-Flop.jpg" alt="Simulated waveform for D Flip Flop" title="Simulated waveform for D Flip Flop" width="564" height="82" class="size-full wp-image-3184" /><figcaption id="caption-attachment-3184" class="wp-caption-text">Simulated waveform for D Flip Flop</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-d-flip-flop/">Verilog HDL Program for D Flip Flop</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Verilog HDL Program for R-S Flip Flops</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-r-s-flip-flops/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-r-s-flip-flops/#comments</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 09 Jun 2012 06:30:04 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[lab programs]]></category>
		<category><![CDATA[R-S Flip Flops]]></category>
		<category><![CDATA[Verilog programs]]></category>
		<category><![CDATA[Verilog lab]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3176</guid>

					<description><![CDATA[<p>A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-r-s-flip-flops/">Verilog HDL Program for R-S Flip Flops</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.</p>
<p>When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.</p>
<p>While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.<br />
<figure id="attachment_3177" aria-describedby="caption-attachment-3177" style="width: 220px" class="wp-caption alignnone"><img decoding="async" loading="lazy" src="https://studentprojects.in/wp-content/uploads/2012/06/RS-Flip-Flop.gif" alt="RS Flip Flop" title="RS Flip Flop" width="220" height="161" class="size-full wp-image-3177" /><figcaption id="caption-attachment-3177" class="wp-caption-text">RS Flip Flop</figcaption></figure></p>
<pre lang="VHDL" line="1">
module srff(q,q1,r,s,clk);
	output q,q1;
	input r,s,clk;
	reg q,q1;
	initial
	begin
		q=1'b0;
		q1=1'b1;
	end
	always @(posedge clk)
	  begin
	  case({s,r})
		 {1'b0,1'b0}: begin q=q; q1=q1; end
		 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
		 {1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
		 {1'b1,1'b1}: begin q=1'bx; q=1'bx; end
	endcase
	end
endmodule
</pre>
<figure id="attachment_3178" aria-describedby="caption-attachment-3178" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" loading="lazy" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-waveform-for-S-R-Flip-Flop.jpg" alt="Simulated waveform for S-R Flip Flop" title="Simulated waveform for S-R Flip Flop" width="615" height="88" class="size-full wp-image-3178" /><figcaption id="caption-attachment-3178" class="wp-caption-text">Simulated waveform for S-R Flip Flop</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-r-s-flip-flops/">Verilog HDL Program for R-S Flip Flops</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Verilog HDL program for 4-BIT Parallel Adder</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-4-bit-parallel-adder/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-4-bit-parallel-adder/#comments</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 02 Jun 2012 07:04:44 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[lab programs]]></category>
		<category><![CDATA[4-BIT Parallel Adder]]></category>
		<category><![CDATA[Verilog program]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3019</guid>

					<description><![CDATA[<p>A 4 bit binary parallel adder can be formed by cascading four full adder units. The carry of each stage is connected to the next unit as the carry in (That is the third input). module parad4(a,c,p,q); output [3:0]a; output c; input [3:0]p,q; wire c1,c2,c3; ha u1(a[0],c1,p[0],q[0]); fa u2(a[1],c2,p[1],q[1],c1); fa u3(a[2],c3,p[2],q[2],c2); fa u4(a[3],c,p[3],q[3],c3); endmodule</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-4-bit-parallel-adder/">Verilog HDL program for 4-BIT Parallel Adder</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>A 4 bit binary parallel adder can be formed by cascading four full adder units. The carry of each stage is connected to the next unit as the carry in (That is the third input).</p>
<pre lang="VHDL" line="1">
module parad4(a,c,p,q);
    output [3:0]a;
    output c;
    input [3:0]p,q;
    wire c1,c2,c3;
    ha u1(a[0],c1,p[0],q[0]);
    fa u2(a[1],c2,p[1],q[1],c1);
    fa u3(a[2],c3,p[2],q[2],c2);
    fa u4(a[3],c,p[3],q[3],c3);
endmodule
</pre>
<figure id="attachment_3020" aria-describedby="caption-attachment-3020" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" loading="lazy" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-waveform-for-Parallel-Adder.jpg" alt="Simulated waveform for Parallel Adder" title="Simulated waveform for Parallel Adder" width="615" height="134" class="size-full wp-image-3020" /><figcaption id="caption-attachment-3020" class="wp-caption-text">Simulated waveform for Parallel Adder</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-4-bit-parallel-adder/">Verilog HDL program for 4-BIT Parallel Adder</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Java program to display triangle 1 24 369 481216</title>
		<link>https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-1-24-369-481216/</link>
					<comments>https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-1-24-369-481216/#comments</comments>
		
		<dc:creator><![CDATA[surajk]]></dc:creator>
		<pubDate>Sat, 05 Feb 2011 13:29:29 +0000</pubDate>
				<category><![CDATA[Basic Programs]]></category>
		<category><![CDATA[Source Codes]]></category>
		<category><![CDATA[Java]]></category>
		<category><![CDATA[lab programs]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=1356</guid>

					<description><![CDATA[<p>/* Display Triangle as follow 1 2 4 3 6 9 4 8 12 16 ... N (indicates no. of Rows) */ class Output3{ public static void main(String args[]){ int n = Integer.parseInt(args[0]); for(int i=1;i</p>
<p>The post <a href="https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-1-24-369-481216/">Java program to display triangle 1 24 369 481216</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<pre lang="java" line="1">
/* Display Triangle as follow<br />
   1<br />
   2 4<br />
   3 6 9<br />
   4 8 12 16 ... N (indicates no. of Rows) */<br />
class Output3{<br />
	public static void main(String args[]){<br />
		int n = Integer.parseInt(args[0]);<br />
		for(int i=1;i<=n;i++){
			for(int j=1;j<=i;j++){
				System.out.print((i*j)+" ");
			}
			System.out.print("\n");
		}
	}
}

</p><p>The post <a href="https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-1-24-369-481216/">Java program to display triangle 1 24 369 481216</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			</item>
		<item>
		<title>Java program to display triangle 0 10 101 0101</title>
		<link>https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-0-10-101-0101/</link>
					<comments>https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-0-10-101-0101/#comments</comments>
		
		<dc:creator><![CDATA[surajk]]></dc:creator>
		<pubDate>Sat, 05 Feb 2011 13:28:49 +0000</pubDate>
				<category><![CDATA[Basic Programs]]></category>
		<category><![CDATA[Source Codes]]></category>
		<category><![CDATA[Java]]></category>
		<category><![CDATA[lab programs]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=1354</guid>

					<description><![CDATA[<p>/* Display Triangle as follow 0 1 0 1 0 1 0 1 0 1 */ class Output2{ public static void main(String args[]){ for(int i=1;i</p>
<p>The post <a href="https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-0-10-101-0101/">Java program to display triangle 0 10 101 0101</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<pre lang="java" line="1">
/* Display Triangle as follow
   0
   1 0
   1 0 1
   0 1 0 1 */
class Output2{
	public static void main(String args[]){
		for(int i=1;i<=4;i++){
			for(int j=1;j<=i;j++){
				System.out.print(((i+j)%2)+" ");
			}
			System.out.print("\n");
		}
	}
}
</pre><p>The post <a href="https://studentprojects.in/software-development/java/java-programs/basic/java-program-display-triangle-0-10-101-0101/">Java program to display triangle 0 10 101 0101</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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			<slash:comments>7</slash:comments>
		
		
			</item>
	</channel>
</rss>
