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	<title>2 - 4 Decoder | Student Projects</title>
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		<title>Verilog HDL program for 2 &#8211; 4 Decoder</title>
		<link>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2-4-decoder/</link>
					<comments>https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2-4-decoder/#comments</comments>
		
		<dc:creator><![CDATA[Ansten Lobo]]></dc:creator>
		<pubDate>Sat, 02 Jun 2012 09:37:19 +0000</pubDate>
				<category><![CDATA[Verilog HDL]]></category>
		<category><![CDATA[2 - 4 Decoder]]></category>
		<category><![CDATA[Verilog lab programs]]></category>
		<guid isPermaLink="false">http://studentprojects.in/?p=3022</guid>

					<description><![CDATA[<p>A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of</p>
<p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2-4-decoder/">Verilog HDL program for 2 – 4 Decoder</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></description>
										<content:encoded><![CDATA[<p>A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.</p>
<pre lang="VHDL" line="1">
module decoder24(c,a,b,e);
    output [3:0]c;
    input a,b,e;
    wire x,y;
    wire [3:0]c1;
    inv u1(x,a);
    inv u2(y,b);
    and1 u3(c1[0],x,y);
    and1 u4(c1[1],x,b);
    and1 u5(c1[2],a,y);
    and1 u6(c1[3],a,b);
    and1 u7(c[0],c1[0],e);
    and1 u8(c[1],c1[1],e);
    and1 u9(c[2],c1[2],e);
    and1 u10(c[3],c1[3],e);
endmodule
</pre>
<figure id="attachment_3023" aria-describedby="caption-attachment-3023" style="width: 615px" class="wp-caption aligncenter"><img decoding="async" src="https://studentprojects.in/wp-content/uploads/2012/06/Simulated-waveform-for-2-4-Decoder.jpg" alt="Simulated waveform for 2-4 Decoder" title="Simulated waveform for 2-4 Decoder" width="615" height="103" class="size-full wp-image-3023" /><figcaption id="caption-attachment-3023" class="wp-caption-text">Simulated waveform for 2-4 Decoder</figcaption></figure><p>The post <a href="https://studentprojects.in/electronics/verilog-hdl/verilog-hdl-program-for-2-4-decoder/">Verilog HDL program for 2 – 4 Decoder</a> first appeared on <a href="https://studentprojects.in">Student Projects</a>.</p>]]></content:encoded>
					
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